106 lines
3.0 KiB
C
106 lines
3.0 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CACHETYPE_H
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#define __ASM_CACHETYPE_H
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#include <asm/cputype.h>
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#define CTR_L1IP_SHIFT 14
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#define CTR_L1IP_MASK 3
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#define CTR_CWG_SHIFT 24
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#define CTR_CWG_MASK 15
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#define CTR_DMINLINE_SHIFT 16
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#define CTR_IMINLINE_SHIFT 0
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#define CTR_CACHE_MINLINE_MASK \
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((0xf << CTR_DMINLINE_SHIFT) | (0xf << CTR_IMINLINE_SHIFT))
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#define ICACHE_POLICY_RESERVED 0
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#define ICACHE_POLICY_AIVIVT 1
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#define ICACHE_POLICY_VIPT 2
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#define ICACHE_POLICY_PIPT 3
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
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#define ICACHEF_ALIASING 0
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#define ICACHEF_AIVIVT 1
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extern unsigned long __icache_flags;
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/*
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* NumSets, bits[27:13] - (Number of sets in cache) - 1
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* Associativity, bits[12:3] - (Associativity of cache) - 1
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* LineSize, bits[2:0] - (Log2(Number of words in cache line)) - 2
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*/
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#define CCSIDR_EL1_WRITE_THROUGH BIT(31)
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#define CCSIDR_EL1_WRITE_BACK BIT(30)
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#define CCSIDR_EL1_READ_ALLOCATE BIT(29)
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#define CCSIDR_EL1_WRITE_ALLOCATE BIT(28)
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#define CCSIDR_EL1_LINESIZE_MASK 0x7
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#define CCSIDR_EL1_LINESIZE(x) ((x) & CCSIDR_EL1_LINESIZE_MASK)
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#define CCSIDR_EL1_ASSOCIATIVITY_SHIFT 3
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#define CCSIDR_EL1_ASSOCIATIVITY_MASK 0x3ff
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#define CCSIDR_EL1_ASSOCIATIVITY(x) \
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(((x) >> CCSIDR_EL1_ASSOCIATIVITY_SHIFT) & CCSIDR_EL1_ASSOCIATIVITY_MASK)
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#define CCSIDR_EL1_NUMSETS_SHIFT 13
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#define CCSIDR_EL1_NUMSETS_MASK 0x7fff
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#define CCSIDR_EL1_NUMSETS(x) \
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(((x) >> CCSIDR_EL1_NUMSETS_SHIFT) & CCSIDR_EL1_NUMSETS_MASK)
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#define CACHE_LINESIZE(x) (16 << CCSIDR_EL1_LINESIZE(x))
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#define CACHE_NUMSETS(x) (CCSIDR_EL1_NUMSETS(x) + 1)
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#define CACHE_ASSOCIATIVITY(x) (CCSIDR_EL1_ASSOCIATIVITY(x) + 1)
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extern u64 __attribute_const__ cache_get_ccsidr(u64 csselr);
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/* Helpers for Level 1 Instruction cache csselr = 1L */
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static inline int icache_get_linesize(void)
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{
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return CACHE_LINESIZE(cache_get_ccsidr(1L));
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}
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static inline int icache_get_numsets(void)
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{
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return CACHE_NUMSETS(cache_get_ccsidr(1L));
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}
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/*
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* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
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* permitted in the I-cache.
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*/
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static inline int icache_is_aliasing(void)
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{
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return test_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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static inline int icache_is_aivivt(void)
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{
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return test_bit(ICACHEF_AIVIVT, &__icache_flags);
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}
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static inline u32 cache_type_cwg(void)
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{
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return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_CACHETYPE_H */
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