mirror of
https://github.com/brain-hackers/linux-brain.git
synced 2024-06-09 23:36:23 +09:00
4166bfe530
Add driver for Amazon's Annapurna Labs PCIe host controller. The controller is based on DesignWare's IP. The controller doesn't support accessing the Root Port's config space via ECAM, so we obtain its base address via an AMZN0001 device. Furthermore, the DesignWare PCIe controller doesn't filter out config transactions sent to devices 1 and up on its bus, so they are filtered by the driver. All subordinate buses do support ECAM access. Implementing specific PCI config access functions involves: - Adding an init function to obtain the Root Port's base address from an AMZN0001 device. - Adding a new entry in the MCFG quirk array. [bhelgaas: Note that there is no Kconfig option for this driver because it is only intended for use with the generic ACPI host bridge driver. This driver is only needed because the DesignWare IP doesn't completely support ECAM access to the root bus.] Link: https://lore.kernel.org/lkml/1553774276-24675-1-git-send-email-jonnyc@amazon.com Co-developed-by: Vladimir Aerov <vaerov@amazon.com> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Vladimir Aerov <vaerov@amazon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright 2016 Broadcom
|
|
*/
|
|
#ifndef DRIVERS_PCI_ECAM_H
|
|
#define DRIVERS_PCI_ECAM_H
|
|
|
|
#include <linux/pci.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/platform_device.h>
|
|
|
|
/*
|
|
* struct to hold pci ops and bus shift of the config window
|
|
* for a PCI controller.
|
|
*/
|
|
struct pci_config_window;
|
|
struct pci_ecam_ops {
|
|
unsigned int bus_shift;
|
|
struct pci_ops pci_ops;
|
|
int (*init)(struct pci_config_window *);
|
|
};
|
|
|
|
/*
|
|
* struct to hold the mappings of a config space window. This
|
|
* is expected to be used as sysdata for PCI controllers that
|
|
* use ECAM.
|
|
*/
|
|
struct pci_config_window {
|
|
struct resource res;
|
|
struct resource busr;
|
|
void *priv;
|
|
struct pci_ecam_ops *ops;
|
|
union {
|
|
void __iomem *win; /* 64-bit single mapping */
|
|
void __iomem **winp; /* 32-bit per-bus mapping */
|
|
};
|
|
struct device *parent;/* ECAM res was from this dev */
|
|
};
|
|
|
|
/* create and free pci_config_window */
|
|
struct pci_config_window *pci_ecam_create(struct device *dev,
|
|
struct resource *cfgres, struct resource *busr,
|
|
struct pci_ecam_ops *ops);
|
|
void pci_ecam_free(struct pci_config_window *cfg);
|
|
|
|
/* map_bus when ->sysdata is an instance of pci_config_window */
|
|
void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
|
|
int where);
|
|
/* default ECAM ops */
|
|
extern struct pci_ecam_ops pci_generic_ecam_ops;
|
|
|
|
#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
|
|
extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
|
|
extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
|
|
extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
|
|
extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
|
|
extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
|
|
extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
|
|
extern struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_HOST_COMMON
|
|
/* for DT-based PCI controllers that support ECAM */
|
|
int pci_host_common_probe(struct platform_device *pdev,
|
|
struct pci_ecam_ops *ops);
|
|
int pci_host_common_remove(struct platform_device *pdev);
|
|
#endif
|
|
#endif
|