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d52888aa27
On 5-level paging the LDT remap area is placed in the middle of the KASLR
randomization region and it can overlap with the direct mapping, the
vmalloc or the vmap area.
The LDT mapping is per mm, so it cannot be moved into the P4D page table
next to the CPU_ENTRY_AREA without complicating PGD table allocation for
5-level paging.
The 4 PGD slot gap just before the direct mapping is reserved for
hypervisors, so it cannot be used.
Move the direct mapping one slot deeper and use the resulting gap for the
LDT remap area. The resulting layout is the same for 4 and 5 level paging.
[ tglx: Massaged changelog ]
Fixes: f55f0501cb ("x86/pti: Put the LDT in its own PGD if PTI is on")
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andy Lutomirski <luto@kernel.org>
Cc: bp@alien8.de
Cc: hpa@zytor.com
Cc: dave.hansen@linux.intel.com
Cc: peterz@infradead.org
Cc: boris.ostrovsky@oracle.com
Cc: jgross@suse.com
Cc: bhe@redhat.com
Cc: willy@infradead.org
Cc: linux-mm@kvack.org
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20181026122856.66224-2-kirill.shutemov@linux.intel.com
158 lines
3.9 KiB
C
158 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PGTABLE_64_DEFS_H
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#define _ASM_X86_PGTABLE_64_DEFS_H
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#include <asm/sparsemem.h>
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/kaslr.h>
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/*
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* These are used to make use of C type-checking..
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*/
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typedef unsigned long pteval_t;
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typedef unsigned long pmdval_t;
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typedef unsigned long pudval_t;
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typedef unsigned long p4dval_t;
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typedef unsigned long pgdval_t;
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typedef unsigned long pgprotval_t;
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typedef struct { pteval_t pte; } pte_t;
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#ifdef CONFIG_X86_5LEVEL
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extern unsigned int __pgtable_l5_enabled;
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#ifdef USE_EARLY_PGTABLE_L5
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/*
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* cpu_feature_enabled() is not available in early boot code.
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* Use variable instead.
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*/
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static inline bool pgtable_l5_enabled(void)
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{
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return __pgtable_l5_enabled;
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}
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#else
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#define pgtable_l5_enabled() cpu_feature_enabled(X86_FEATURE_LA57)
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#endif /* USE_EARLY_PGTABLE_L5 */
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#else
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#define pgtable_l5_enabled() 0
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#endif /* CONFIG_X86_5LEVEL */
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extern unsigned int pgdir_shift;
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extern unsigned int ptrs_per_p4d;
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#endif /* !__ASSEMBLY__ */
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#define SHARED_KERNEL_PMD 0
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#ifdef CONFIG_X86_5LEVEL
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/*
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* PGDIR_SHIFT determines what a top-level page table entry can map
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*/
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#define PGDIR_SHIFT pgdir_shift
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#define PTRS_PER_PGD 512
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/*
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* 4th level page in 5-level paging case
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*/
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#define P4D_SHIFT 39
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#define MAX_PTRS_PER_P4D 512
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#define PTRS_PER_P4D ptrs_per_p4d
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#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
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#define P4D_MASK (~(P4D_SIZE - 1))
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#define MAX_POSSIBLE_PHYSMEM_BITS 52
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#else /* CONFIG_X86_5LEVEL */
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/*
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* PGDIR_SHIFT determines what a top-level page table entry can map
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*/
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#define PGDIR_SHIFT 39
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#define PTRS_PER_PGD 512
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#define MAX_PTRS_PER_P4D 1
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#endif /* CONFIG_X86_5LEVEL */
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/*
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* 3rd level page
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*/
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#define PUD_SHIFT 30
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#define PTRS_PER_PUD 512
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/*
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* PMD_SHIFT determines the size of the area a middle-level
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* page table can map
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*/
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#define PMD_SHIFT 21
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#define PTRS_PER_PMD 512
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/*
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* entries per page directory level
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*/
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#define PTRS_PER_PTE 512
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#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE - 1))
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#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE - 1))
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#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE - 1))
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/*
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* See Documentation/x86/x86_64/mm.txt for a description of the memory map.
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*
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* Be very careful vs. KASLR when changing anything here. The KASLR address
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* range must not overlap with anything except the KASAN shadow area, which
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* is correct as KASAN disables KASLR.
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*/
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#define MAXMEM (1UL << MAX_PHYSMEM_BITS)
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#define LDT_PGD_ENTRY -240UL
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#define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT)
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#define LDT_END_ADDR (LDT_BASE_ADDR + PGDIR_SIZE)
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#define __VMALLOC_BASE_L4 0xffffc90000000000UL
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#define __VMALLOC_BASE_L5 0xffa0000000000000UL
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#define VMALLOC_SIZE_TB_L4 32UL
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#define VMALLOC_SIZE_TB_L5 12800UL
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#define __VMEMMAP_BASE_L4 0xffffea0000000000UL
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#define __VMEMMAP_BASE_L5 0xffd4000000000000UL
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#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
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# define VMALLOC_START vmalloc_base
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# define VMALLOC_SIZE_TB (pgtable_l5_enabled() ? VMALLOC_SIZE_TB_L5 : VMALLOC_SIZE_TB_L4)
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# define VMEMMAP_START vmemmap_base
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#else
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# define VMALLOC_START __VMALLOC_BASE_L4
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# define VMALLOC_SIZE_TB VMALLOC_SIZE_TB_L4
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# define VMEMMAP_START __VMEMMAP_BASE_L4
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#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
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#define VMALLOC_END (VMALLOC_START + (VMALLOC_SIZE_TB << 40) - 1)
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#define MODULES_VADDR (__START_KERNEL_map + KERNEL_IMAGE_SIZE)
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/* The module sections ends with the start of the fixmap */
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#define MODULES_END _AC(0xffffffffff000000, UL)
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#define MODULES_LEN (MODULES_END - MODULES_VADDR)
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#define ESPFIX_PGD_ENTRY _AC(-2, UL)
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#define ESPFIX_BASE_ADDR (ESPFIX_PGD_ENTRY << P4D_SHIFT)
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#define CPU_ENTRY_AREA_PGD _AC(-4, UL)
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#define CPU_ENTRY_AREA_BASE (CPU_ENTRY_AREA_PGD << P4D_SHIFT)
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#define EFI_VA_START ( -4 * (_AC(1, UL) << 30))
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#define EFI_VA_END (-68 * (_AC(1, UL) << 30))
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#define EARLY_DYNAMIC_PAGE_TABLES 64
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#define PGD_KERNEL_START ((PAGE_SIZE / 2) / sizeof(pgd_t))
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#endif /* _ASM_X86_PGTABLE_64_DEFS_H */
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