237 lines
5.3 KiB
C
237 lines
5.3 KiB
C
/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include "clk.h"
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/**
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* struct clk_dfs - S32 DFS clock
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* @clk_hw: clock source
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* @reg: DFS register address
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* @idx: the index of DFS encoded in the register
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*
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* DFS clock found on S32 series. Each register for DFS has 4 clk_dfs
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* data encoded, and member idx is used to specify the one.
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* Only ARMPLL(3 DFS), ENETPLL(4 DFS) and DDRPLL(3 DFS) has DFS outputs.
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*/
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struct clk_dfs {
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struct clk_hw hw;
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void __iomem *reg;
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enum s32v234_plldig_type plltype;
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u8 idx;
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u32 mfn;
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};
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#define to_clk_dfs(_hw) container_of(_hw, struct clk_dfs, hw)
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static int get_pllx_dfs_nr(enum s32v234_plldig_type plltype)
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{
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switch (plltype) {
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case S32_PLLDIG_ARM:
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return ARMPLL_DFS_NR;
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case S32_PLLDIG_ENET:
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return ENETPLL_DFS_NR;
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case S32_PLLDIG_DDR:
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return DDRPLL_DFS_NR;
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case S32_PLLDIG_PERIPH:
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case S32_PLLDIG_VIDEO:
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pr_warn("Current selected PLL has no DFS\n");
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break;
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}
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return -EINVAL;
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}
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static unsigned long get_pllx_dfsy_max_rate(enum s32v234_plldig_type plltype,
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int dfsno)
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{
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switch (plltype) {
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case S32_PLLDIG_ARM:
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switch (dfsno) {
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case 0:
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return ARMPLL_DFS0_MAX_RATE;
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case 1:
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return ARMPLL_DFS1_MAX_RATE;
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case 2:
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return ARMPLL_DFS2_MAX_RATE;
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}
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break;
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case S32_PLLDIG_ENET:
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switch (dfsno) {
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case 0:
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return ENETPLL_DFS0_MAX_RATE;
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case 1:
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return ENETPLL_DFS1_MAX_RATE;
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case 2:
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return ENETPLL_DFS2_MAX_RATE;
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case 3:
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return ENETPLL_DFS3_MAX_RATE;
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}
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break;
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case S32_PLLDIG_DDR:
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switch (dfsno) {
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case 0:
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return DDRPLL_DFS0_MAX_RATE;
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case 1:
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return DDRPLL_DFS1_MAX_RATE;
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case 2:
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return DDRPLL_DFS2_MAX_RATE;
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}
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break;
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case S32_PLLDIG_PERIPH:
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case S32_PLLDIG_VIDEO:
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pr_warn("Current selected PLL has no DFS.");
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break;
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default:
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pr_warn("Unsupported PLL. Use %d or %d\n",
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S32_PLLDIG_ARM, S32_PLLDIG_VIDEO);
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break;
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}
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return -EINVAL;
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}
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static int clk_dfs_enable(struct clk_hw *hw)
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{
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/*
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* TODO: When SOC is available, this function
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* should be tested and implemented for DFS
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* if it is possible
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*/
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return 0;
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}
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static void clk_dfs_disable(struct clk_hw *hw)
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{
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/*
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* TODO: When SOC is available, this function
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* should be tested and implemented for DFS
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* if it is possible
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*/
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}
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static unsigned long clk_dfs_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_dfs *dfs = to_clk_dfs(hw);
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u32 mfn, mfi, rate;
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u32 dvport = readl_relaxed(DFS_DVPORTn(dfs->reg, dfs->idx));
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mfn = (dvport & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_OFFSET;
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mfi = (dvport & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_OFFSET;
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mfi <<= 8;
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rate = parent_rate / (mfi + mfn);
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rate <<= 8;
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return rate;
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}
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static long clk_dfs_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_dfs *dfs = to_clk_dfs(hw);
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unsigned long max_allowed_rate;
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max_allowed_rate = get_pllx_dfsy_max_rate(dfs->plltype, dfs->idx);
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if (rate > max_allowed_rate)
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rate = max_allowed_rate;
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return rate;
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}
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static int clk_dfs_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_dfs *dfs = to_clk_dfs(hw);
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u32 mfi;
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u32 portreset = readl_relaxed(DFS_PORTRESET(dfs->reg));
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writel_relaxed(DFS_CTRL_DLL_RESET, DFS_CTRL(dfs->reg));
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writel_relaxed(portreset | ~DFS_PORTRESET_PORTRESET_SET(dfs->idx),
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DFS_PORTRESET(dfs->reg));
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mfi = parent_rate/rate;
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writel_relaxed(DFS_DVPORTn_MFI_SET(mfi) |
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DFS_DVPORTn_MFN_SET(dfs->mfn),
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DFS_DVPORTn(dfs->reg, dfs->idx));
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writel_relaxed(~DFS_CTRL_DLL_RESET, DFS_CTRL(dfs->reg));
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while (readl_relaxed(DFS_PORTSR(dfs->reg)) & (1 << (dfs->idx)))
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;
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return 0;
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}
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static int clk_dfs_is_enabled(struct clk_hw *hw)
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{
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struct clk_dfs *dfs = to_clk_dfs(hw);
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/* Check if current DFS output port is locked */
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if (readl_relaxed(DFS_PORTSR(dfs->reg)) & (1 << (dfs->idx)))
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return 0;
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return 1;
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}
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static const struct clk_ops clk_dfs_ops = {
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.enable = clk_dfs_enable,
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.disable = clk_dfs_disable,
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.recalc_rate = clk_dfs_recalc_rate,
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.round_rate = clk_dfs_round_rate,
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.set_rate = clk_dfs_set_rate,
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.is_enabled = clk_dfs_is_enabled,
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};
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struct clk *s32v234_clk_dfs(enum s32v234_plldig_type type, const char *name,
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const char *parent_name, void __iomem *reg,
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u8 idx, u32 mfn)
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{
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struct clk_dfs *dfs;
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struct clk *clk;
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struct clk_init_data init;
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/* PERIPH and VIDEO PLL do not have DFS */
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if (type == S32_PLLDIG_PERIPH || type == S32_PLLDIG_VIDEO)
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return ERR_PTR(-EINVAL);
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/* check if DFS index is valid for current pll */
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if (idx >= get_pllx_dfs_nr(type))
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return ERR_PTR(-EINVAL);
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dfs = kzalloc(sizeof(*dfs), GFP_KERNEL);
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if (!dfs)
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return ERR_PTR(-ENOMEM);
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dfs->reg = reg;
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dfs->idx = idx;
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dfs->mfn = mfn;
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dfs->plltype = type;
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init.name = name;
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init.ops = &clk_dfs_ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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dfs->hw.init = &init;
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clk = clk_register(NULL, &dfs->hw);
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if (IS_ERR(clk))
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kfree(dfs);
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return clk;
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}
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