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e879b7ab37
GMAC_INT_DEFAULT_MASK is written to the interrupt enable register. In previous versions of the IP (e.g. dwmac1000), this register was instead an interrupt mask register. To improve clarity and reflect reality, rename GMAC_INT_DEFAULT_MASK to GMAC_INT_DEFAULT_ENABLE. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: David S. Miller <davem@davemloft.net>
401 lines
13 KiB
C
401 lines
13 KiB
C
/*
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* DWMAC4 Header file.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#ifndef __DWMAC4_H__
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#define __DWMAC4_H__
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#include "common.h"
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/* MAC registers */
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#define GMAC_CONFIG 0x00000000
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#define GMAC_PACKET_FILTER 0x00000008
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#define GMAC_HASH_TAB_0_31 0x00000010
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#define GMAC_HASH_TAB_32_63 0x00000014
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#define GMAC_RX_FLOW_CTRL 0x00000090
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#define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
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#define GMAC_TXQ_PRTY_MAP0 0x98
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#define GMAC_TXQ_PRTY_MAP1 0x9C
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#define GMAC_RXQ_CTRL0 0x000000a0
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#define GMAC_RXQ_CTRL1 0x000000a4
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#define GMAC_RXQ_CTRL2 0x000000a8
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#define GMAC_RXQ_CTRL3 0x000000ac
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#define GMAC_INT_STATUS 0x000000b0
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#define GMAC_INT_EN 0x000000b4
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#define GMAC_1US_TIC_COUNTER 0x000000dc
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#define GMAC_PCS_BASE 0x000000e0
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#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
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#define GMAC_PMT 0x000000c0
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#define GMAC_VERSION 0x00000110
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#define GMAC_DEBUG 0x00000114
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#define GMAC_HW_FEATURE0 0x0000011c
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#define GMAC_HW_FEATURE1 0x00000120
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#define GMAC_HW_FEATURE2 0x00000124
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#define GMAC_MDIO_ADDR 0x00000200
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#define GMAC_MDIO_DATA 0x00000204
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#define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
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#define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
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/* RX Queues Routing */
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#define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
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#define GMAC_RXQCTRL_AVCPQ_SHIFT 0
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#define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
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#define GMAC_RXQCTRL_PTPQ_SHIFT 4
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#define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
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#define GMAC_RXQCTRL_DCBCPQ_SHIFT 8
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#define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
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#define GMAC_RXQCTRL_UPQ_SHIFT 12
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#define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
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#define GMAC_RXQCTRL_MCBCQ_SHIFT 16
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#define GMAC_RXQCTRL_MCBCQEN BIT(20)
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#define GMAC_RXQCTRL_MCBCQEN_SHIFT 20
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#define GMAC_RXQCTRL_TACPQE BIT(21)
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#define GMAC_RXQCTRL_TACPQE_SHIFT 21
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/* MAC Packet Filtering */
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#define GMAC_PACKET_FILTER_PR BIT(0)
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#define GMAC_PACKET_FILTER_HMC BIT(2)
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#define GMAC_PACKET_FILTER_PM BIT(4)
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#define GMAC_MAX_PERFECT_ADDRESSES 128
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/* MAC RX Queue Enable */
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#define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
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#define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
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#define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
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/* MAC Flow Control RX */
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#define GMAC_RX_FLOW_CTRL_RFE BIT(0)
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/* RX Queues Priorities */
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#define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
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#define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8)
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/* TX Queues Priorities */
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#define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
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#define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8)
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/* MAC Flow Control TX */
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#define GMAC_TX_FLOW_CTRL_TFE BIT(1)
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#define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
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/* MAC Interrupt bitmap*/
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#define GMAC_INT_RGSMIIS BIT(0)
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#define GMAC_INT_PCS_LINK BIT(1)
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#define GMAC_INT_PCS_ANE BIT(2)
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#define GMAC_INT_PCS_PHYIS BIT(3)
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#define GMAC_INT_PMT_EN BIT(4)
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#define GMAC_INT_LPI_EN BIT(5)
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#define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
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GMAC_INT_PCS_ANE)
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#define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN)
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enum dwmac4_irq_status {
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time_stamp_irq = 0x00001000,
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mmc_rx_csum_offload_irq = 0x00000800,
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mmc_tx_irq = 0x00000400,
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mmc_rx_irq = 0x00000200,
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mmc_irq = 0x00000100,
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lpi_irq = 0x00000020,
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pmt_irq = 0x00000010,
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};
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/* MAC PMT bitmap */
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enum power_event {
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pointer_reset = 0x80000000,
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global_unicast = 0x00000200,
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wake_up_rx_frame = 0x00000040,
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magic_frame = 0x00000020,
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wake_up_frame_en = 0x00000004,
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magic_pkt_en = 0x00000002,
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power_down = 0x00000001,
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};
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/* Energy Efficient Ethernet (EEE) for GMAC4
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*
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* LPI status, timer and control register offset
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*/
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#define GMAC4_LPI_CTRL_STATUS 0xd0
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#define GMAC4_LPI_TIMER_CTRL 0xd4
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/* LPI control and status defines */
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#define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
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#define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
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#define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
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#define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
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#define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
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#define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
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#define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
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#define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
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/* MAC Debug bitmap */
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#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
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#define GMAC_DEBUG_TFCSTS_SHIFT 17
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#define GMAC_DEBUG_TFCSTS_IDLE 0
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#define GMAC_DEBUG_TFCSTS_WAIT 1
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#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
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#define GMAC_DEBUG_TFCSTS_XFER 3
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#define GMAC_DEBUG_TPESTS BIT(16)
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#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
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#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
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#define GMAC_DEBUG_RPESTS BIT(0)
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/* MAC config */
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#define GMAC_CONFIG_IPC BIT(27)
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#define GMAC_CONFIG_2K BIT(22)
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#define GMAC_CONFIG_ACS BIT(20)
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#define GMAC_CONFIG_BE BIT(18)
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#define GMAC_CONFIG_JD BIT(17)
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#define GMAC_CONFIG_JE BIT(16)
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#define GMAC_CONFIG_PS BIT(15)
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#define GMAC_CONFIG_FES BIT(14)
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#define GMAC_CONFIG_DM BIT(13)
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#define GMAC_CONFIG_DCRS BIT(9)
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#define GMAC_CONFIG_TE BIT(1)
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#define GMAC_CONFIG_RE BIT(0)
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/* MAC HW features0 bitmap */
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#define GMAC_HW_FEAT_ADDMAC BIT(18)
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#define GMAC_HW_FEAT_RXCOESEL BIT(16)
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#define GMAC_HW_FEAT_TXCOSEL BIT(14)
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#define GMAC_HW_FEAT_EEESEL BIT(13)
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#define GMAC_HW_FEAT_TSSEL BIT(12)
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#define GMAC_HW_FEAT_MMCSEL BIT(8)
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#define GMAC_HW_FEAT_MGKSEL BIT(7)
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#define GMAC_HW_FEAT_RWKSEL BIT(6)
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#define GMAC_HW_FEAT_SMASEL BIT(5)
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#define GMAC_HW_FEAT_VLHASH BIT(4)
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#define GMAC_HW_FEAT_PCSSEL BIT(3)
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#define GMAC_HW_FEAT_HDSEL BIT(2)
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#define GMAC_HW_FEAT_GMIISEL BIT(1)
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#define GMAC_HW_FEAT_MIISEL BIT(0)
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/* MAC HW features1 bitmap */
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#define GMAC_HW_FEAT_AVSEL BIT(20)
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#define GMAC_HW_TSOEN BIT(18)
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#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
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#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
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/* MAC HW features2 bitmap */
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#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
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#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
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#define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
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#define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
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/* MAC HW ADDR regs */
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#define GMAC_HI_DCS GENMASK(18, 16)
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#define GMAC_HI_DCS_SHIFT 16
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#define GMAC_HI_REG_AE BIT(31)
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/* MTL registers */
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#define MTL_OPERATION_MODE 0x00000c00
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#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
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#define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
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#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
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#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
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#define MTL_OPERATION_SCHALG_SP (0x3 << 5)
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#define MTL_OPERATION_RAA BIT(2)
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#define MTL_OPERATION_RAA_SP (0x0 << 2)
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#define MTL_OPERATION_RAA_WSP (0x1 << 2)
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#define MTL_INT_STATUS 0x00000c20
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#define MTL_INT_QX(x) BIT(x)
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#define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
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#define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
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#define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0)
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#define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0)
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#define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
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#define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
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#define MTL_CHAN_BASE_ADDR 0x00000d00
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#define MTL_CHAN_BASE_OFFSET 0x40
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#define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \
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(x * MTL_CHAN_BASE_OFFSET))
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#define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x)
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#define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8)
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#define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c)
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#define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30)
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#define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38)
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#define MTL_OP_MODE_RSF BIT(5)
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#define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)
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#define MTL_OP_MODE_TXQEN_AV BIT(2)
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#define MTL_OP_MODE_TXQEN BIT(3)
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#define MTL_OP_MODE_TSF BIT(1)
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#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
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#define MTL_OP_MODE_TQS_SHIFT 16
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#define MTL_OP_MODE_TTC_MASK 0x70
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#define MTL_OP_MODE_TTC_SHIFT 4
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#define MTL_OP_MODE_TTC_32 0
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#define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
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#define MTL_OP_MODE_RQS_SHIFT 20
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#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
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#define MTL_OP_MODE_RFD_SHIFT 14
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#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
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#define MTL_OP_MODE_RFA_SHIFT 8
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#define MTL_OP_MODE_EHFC BIT(7)
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#define MTL_OP_MODE_RTC_MASK 0x18
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#define MTL_OP_MODE_RTC_SHIFT 3
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#define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
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#define MTL_OP_MODE_RTC_64 0
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#define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
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#define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
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/* MTL ETS Control register */
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#define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
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#define MTL_ETS_CTRL_BASE_OFFSET 0x40
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#define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \
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((x) * MTL_ETS_CTRL_BASE_OFFSET))
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#define MTL_ETS_CTRL_CC BIT(3)
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#define MTL_ETS_CTRL_AVALG BIT(2)
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/* MTL Queue Quantum Weight */
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#define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18
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#define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40
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#define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \
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((x) * MTL_TXQ_WEIGHT_BASE_OFFSET))
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#define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
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/* MTL sendSlopeCredit register */
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#define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c
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#define MTL_SEND_SLP_CRED_OFFSET 0x40
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#define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \
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((x) * MTL_SEND_SLP_CRED_OFFSET))
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#define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
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/* MTL hiCredit register */
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#define MTL_HIGH_CRED_BASE_ADDR 0x00000d20
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#define MTL_HIGH_CRED_OFFSET 0x40
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#define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \
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((x) * MTL_HIGH_CRED_OFFSET))
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#define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)
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/* MTL loCredit register */
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#define MTL_LOW_CRED_BASE_ADDR 0x00000d24
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#define MTL_LOW_CRED_OFFSET 0x40
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#define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \
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((x) * MTL_LOW_CRED_OFFSET))
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#define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)
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/* MTL debug */
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#define MTL_DEBUG_TXSTSFSTS BIT(5)
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#define MTL_DEBUG_TXFSTS BIT(4)
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#define MTL_DEBUG_TWCSTS BIT(3)
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/* MTL debug: Tx FIFO Read Controller Status */
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#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_TRCSTS_SHIFT 1
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#define MTL_DEBUG_TRCSTS_IDLE 0
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#define MTL_DEBUG_TRCSTS_READ 1
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#define MTL_DEBUG_TRCSTS_TXW 2
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#define MTL_DEBUG_TRCSTS_WRITE 3
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#define MTL_DEBUG_TXPAUSED BIT(0)
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/* MAC debug: GMII or MII Transmit Protocol Engine Status */
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#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
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#define MTL_DEBUG_RXFSTS_SHIFT 4
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#define MTL_DEBUG_RXFSTS_EMPTY 0
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#define MTL_DEBUG_RXFSTS_BT 1
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#define MTL_DEBUG_RXFSTS_AT 2
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#define MTL_DEBUG_RXFSTS_FULL 3
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#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_RRCSTS_SHIFT 1
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#define MTL_DEBUG_RRCSTS_IDLE 0
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#define MTL_DEBUG_RRCSTS_RDATA 1
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#define MTL_DEBUG_RRCSTS_RSTAT 2
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#define MTL_DEBUG_RRCSTS_FLUSH 3
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#define MTL_DEBUG_RWCSTS BIT(0)
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/* MTL interrupt */
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#define MTL_RX_OVERFLOW_INT_EN BIT(24)
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#define MTL_RX_OVERFLOW_INT BIT(16)
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/* Default operating mode of the MAC */
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#define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \
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GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
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/* To dump the core regs excluding the Address Registers */
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#define GMAC_REG_NUM 132
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/* MTL debug */
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#define MTL_DEBUG_TXSTSFSTS BIT(5)
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#define MTL_DEBUG_TXFSTS BIT(4)
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#define MTL_DEBUG_TWCSTS BIT(3)
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/* MTL debug: Tx FIFO Read Controller Status */
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#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_TRCSTS_SHIFT 1
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#define MTL_DEBUG_TRCSTS_IDLE 0
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#define MTL_DEBUG_TRCSTS_READ 1
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#define MTL_DEBUG_TRCSTS_TXW 2
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#define MTL_DEBUG_TRCSTS_WRITE 3
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#define MTL_DEBUG_TXPAUSED BIT(0)
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/* MAC debug: GMII or MII Transmit Protocol Engine Status */
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#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
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#define MTL_DEBUG_RXFSTS_SHIFT 4
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#define MTL_DEBUG_RXFSTS_EMPTY 0
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#define MTL_DEBUG_RXFSTS_BT 1
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#define MTL_DEBUG_RXFSTS_AT 2
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#define MTL_DEBUG_RXFSTS_FULL 3
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#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_RRCSTS_SHIFT 1
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#define MTL_DEBUG_RRCSTS_IDLE 0
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#define MTL_DEBUG_RRCSTS_RDATA 1
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#define MTL_DEBUG_RRCSTS_RSTAT 2
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#define MTL_DEBUG_RRCSTS_FLUSH 3
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#define MTL_DEBUG_RWCSTS BIT(0)
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/* SGMII/RGMII status register */
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#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
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#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
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#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
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#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
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#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
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#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
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#define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
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#define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
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#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
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/* LNKMOD */
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#define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1
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/* LNKSPEED */
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#define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
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#define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
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#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
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extern const struct stmmac_dma_ops dwmac4_dma_ops;
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extern const struct stmmac_dma_ops dwmac410_dma_ops;
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#endif /* __DWMAC4_H__ */
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