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f503843f85
Enable the PCIE EP RC for iMX - hw setup: * two imx boards, one is used as pcie rc, the other is used as pcie ep. RC TX N/P <--> EP RX N/P RX N/P <--> EP TX N/P - sw setup: * when build rc image, make sure that CONFIG_PCI_IMX6=y CONFIG_RC_MODE_IN_EP_RC_SYS=y * when build ep image CONFIG_PCI_IMX6=y CONFIG_EP_MODE_IN_EP_RC_SYS=y - features: * set-up link between rc and ep by their stand-alone ref clk running internally. * in ep's system, ep can access the reserved ddr memory (default address:0x4000_0000 on imx6q sd board, and 0xb000_0000 on imx6sx sdb and imx7d arm2 boards) of pcie rc's system, by the interconnection between pcie ep and pcie rc. * provide one example, howto configure the bar# of ep and so on, when pcie ep emaluates one memory ram ep device * setup one new outbound memory region at rc side, let imx pcie rc can access the memory of imx pcie ep in imx pcie rc ep validation system. - NOTE: * boot up ep platform firstly, then boot up rc platform. * For imx6q/6dl/6sx/7d sabresd boards, make sure that mem=768M is contained in the kernel command line, since the start address of the upper 256mb of the 1g ddr mem is reserved to do the pcie ep rc access operations in default. - RC access memory of EP: - EP: write the <ddr_region_address> to the bar0 of ep. echo <ddr_region_address> > /sys/devices/.../pcie/ep_bar0_addr - RC: access the <pcie_mem_base_addr>, and this address would be mapped to the <ddr_region_address> of ep. - Note: ddr_region_address pcie_mem_base_addr bar0_addr imx6qdl 0x4000_0000 0x0100_0000 0x01ff_c010 imx6sx 0xb000_0000 0x0800_0000 0x08ff_c010 imx7d 0xb000_0000 0x4000_0000 0x3380_0010 imx8mq 0xb820_0000 0x2000_0000 0x33c0_0010 imx8mm 0xb820_0000 0x1800_0000 0x3380_0010 imx8qm 0x9020_0000 0x6000_0000 0x5f00_0010 imx8qxp 0x9020_0000 0x7000_0000 0x5f01_0010 - The example of the RC access memory of EP step1: EP side: echo 0x90200000 > /sys/devices/platform/bus@5f000000/5f000000.pcie /ep_bar0_addr root@imx8_all:~# ./memtool 90200000 4 Reading 0x4 count starting at address 0x90200000 0x90200000: 00000000 00000000 00000000 00000000 RC side: ./memtool 60000000=55aa55aa Writing 32-bit value 0x55AA55AA to address 0x60000000 EP side: root@imx8_all:~# ./memtool 90200000 4 Reading 0x4 count starting at address 0x90200000 0x90200000: 55AA55AA 00000000 00000000 00000000 Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
293 lines
9.1 KiB
Plaintext
293 lines
9.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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menu "DesignWare PCI Core Support"
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depends on PCI
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config PCIE_DW
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bool
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config PCIE_DW_HOST
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bool
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW
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config PCIE_DW_EP
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bool
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depends on PCI_ENDPOINT
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select PCIE_DW
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config PCI_DRA7XX
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bool
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config PCI_DRA7XX_HOST
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bool "TI DRA7xx PCIe controller Host Mode"
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depends on SOC_DRA7XX || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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depends on OF && HAS_IOMEM && TI_PIPE3
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select PCIE_DW_HOST
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select PCI_DRA7XX
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default y
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help
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Enables support for the PCIe controller in the DRA7xx SoC to work in
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host mode. There are two instances of PCIe controller in DRA7xx.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCI_DRA7XX_HOST must be selected and in order
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to enable device-specific features PCI_DRA7XX_EP must be selected.
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This uses the DesignWare core.
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config PCI_DRA7XX_EP
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bool "TI DRA7xx PCIe controller Endpoint Mode"
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depends on SOC_DRA7XX || COMPILE_TEST
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depends on PCI_ENDPOINT
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depends on OF && HAS_IOMEM && TI_PIPE3
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select PCIE_DW_EP
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select PCI_DRA7XX
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help
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Enables support for the PCIe controller in the DRA7xx SoC to work in
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endpoint mode. There are two instances of PCIe controller in DRA7xx.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCI_DRA7XX_HOST must be selected and in order
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to enable device-specific features PCI_DRA7XX_EP must be selected.
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This uses the DesignWare core.
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config PCIE_DW_PLAT
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bool
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config PCIE_DW_PLAT_HOST
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bool "Platform bus based DesignWare PCIe Controller - Host mode"
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depends on PCI && PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCIE_DW_PLAT
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help
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Enables support for the PCIe controller in the Designware IP to
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work in host mode. There are two instances of PCIe controller in
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Designware IP.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCIE_DW_PLAT_HOST must be selected and in
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order to enable device-specific features PCI_DW_PLAT_EP must be
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selected.
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config PCIE_DW_PLAT_EP
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bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
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depends on PCI && PCI_MSI_IRQ_DOMAIN
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_DW_PLAT
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help
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Enables support for the PCIe controller in the Designware IP to
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work in endpoint mode. There are two instances of PCIe controller
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in Designware IP.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCIE_DW_PLAT_HOST must be selected and in
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order to enable device-specific features PCI_DW_PLAT_EP must be
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selected.
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config PCI_EXYNOS
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bool "Samsung Exynos PCIe controller"
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depends on SOC_EXYNOS5440 || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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config PCI_IMX6
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bool "Freescale i.MX6/7/8 PCIe controller"
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depends on ARCH_MXC || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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config PCI_IMX6_COMPLIANCE_TEST
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bool "Enable pcie compliance tests on imx6"
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depends on PCI_IMX6
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default n
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help
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Say Y here if you want do the compliance tests on imx6 pcie rc found
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on FSL iMX SoCs.
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config EP_MODE_IN_EP_RC_SYS
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bool "PCI Express EP mode in the IMX6 RC/EP interconnection system"
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depends on PCI_IMX6
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config RC_MODE_IN_EP_RC_SYS
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bool "PCI Express RC mode in the IMX6 RC/EP interconnection system"
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depends on PCI_IMX6 && EP_MODE_IN_EP_RC_SYS!=y
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config PCI_IMX6_EP
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bool "i.MX6 PCI Express EP skeleton driver"
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depends on RC_MODE_IN_EP_RC_SYS
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default y
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config PCIE_SPEAR13XX
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bool "STMicroelectronics SPEAr PCIe controller"
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depends on ARCH_SPEAR13XX || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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config PCI_KEYSTONE
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bool
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config PCI_KEYSTONE_HOST
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bool "PCI Keystone Host Mode"
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depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCI_KEYSTONE
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default y
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help
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Enables support for the PCIe controller in the Keystone SoC to
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work in host mode. The PCI controller on Keystone is based on
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DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_KEYSTONE_EP
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bool "PCI Keystone Endpoint Mode"
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depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCI_KEYSTONE
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help
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Enables support for the PCIe controller in the Keystone SoC to
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work in endpoint mode. The PCI controller on Keystone is based
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on DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_LAYERSCAPE
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bool "Freescale Layerscape PCIe controller - Host mode"
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depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select MFD_SYSCON
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select PCIE_DW_HOST
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help
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Say Y here if you want to enable PCIe controller support on Layerscape
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SoCs to work in Host mode.
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This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
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determines which PCIe controller works in EP mode and which PCIe
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controller works in RC mode.
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config PCI_LAYERSCAPE_EP
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bool "Freescale Layerscape PCIe controller - Endpoint mode"
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depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Say Y here if you want to enable PCIe controller support on Layerscape
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SoCs to work in Endpoint mode.
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This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
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determines which PCIe controller works in EP mode and which PCIe
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controller works in RC mode.
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config PCI_HISI
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depends on OF && (ARM64 || COMPILE_TEST)
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bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCI_HOST_COMMON
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help
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Say Y here if you want PCIe controller support on HiSilicon
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Hip05 and Hip06 SoCs
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config PCIE_QCOM
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bool "Qualcomm PCIe controller"
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here to enable PCIe controller support on Qualcomm SoCs. The
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PCIe controller uses the DesignWare core plus Qualcomm-specific
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hardware wrappers.
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config PCIE_ARMADA_8K
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bool "Marvell Armada-8K PCIe controller"
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depends on ARCH_MVEBU || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want to enable PCIe controller support on
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Armada-8K SoCs. The PCIe controller on Armada-8K is based on
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DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCIE_ARTPEC6
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bool
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config PCIE_ARTPEC6_HOST
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bool "Axis ARTPEC-6 PCIe controller Host Mode"
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depends on MACH_ARTPEC6 || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCIE_ARTPEC6
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help
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Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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host mode. This uses the DesignWare core.
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config PCIE_ARTPEC6_EP
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bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
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depends on MACH_ARTPEC6 || COMPILE_TEST
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_ARTPEC6
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help
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Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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endpoint mode. This uses the DesignWare core.
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config PCIE_KIRIN
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depends on OF && (ARM64 || COMPILE_TEST)
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bool "HiSilicon Kirin series SoCs PCIe controllers"
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support
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on HiSilicon Kirin series SoCs.
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config PCIE_HISI_STB
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bool "HiSilicon STB SoCs PCIe controllers"
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depends on ARCH_HISI || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on HiSilicon STB SoCs
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config PCI_MESON
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bool "MESON PCIe controller"
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want to enable PCI controller support on Amlogic
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SoCs. The PCI controller on Amlogic is based on DesignWare hardware
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and therefore the driver re-uses the DesignWare core functions to
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implement the driver.
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config PCIE_TEGRA194
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tristate "NVIDIA Tegra194 (and later) PCIe controller"
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depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PHY_TEGRA194_P2U
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help
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Say Y here if you want support for DesignWare core based PCIe host
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controller found in NVIDIA Tegra194 SoC.
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config PCIE_UNIPHIER
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bool "Socionext UniPhier PCIe controllers"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on UniPhier SoCs.
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This driver supports LD20 and PXs3 SoCs.
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config PCIE_AL
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bool "Amazon Annapurna Labs PCIe controller"
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depends on OF && (ARM64 || COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here to enable support of the Amazon's Annapurna Labs PCIe
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controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
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core plus Annapurna Labs proprietary hardware wrappers. This is
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required only for DT-based platforms. ACPI platforms with the
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Annapurna Labs PCIe controller don't need to enable this.
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endmenu
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