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bf4289cba0
So we can now choose for the board the ecc mode (ecc soft, soft bch, no ecc and hardware). Set ecc mode in the boards to soft as currently in the driver. Move platform data to a common header include/linux/platform_data/atmel_nand.h Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no> Acked-by: David Woodhouse <dwmw2@infradead.org>
325 lines
8.4 KiB
C
325 lines
8.4 KiB
C
/*
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* Board-specific setup code for the ATNGW100 Network Gateway
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*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/etherdevice.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/i2c.h>
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#include <linux/i2c-gpio.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/leds.h>
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#include <linux/spi/spi.h>
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#include <linux/atmel-mci.h>
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#include <linux/usb/atmel_usba_udc.h>
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#include <asm/io.h>
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#include <asm/setup.h>
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#include <mach/at32ap700x.h>
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#include <mach/board.h>
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#include <mach/init.h>
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#include <mach/portmux.h>
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/* Oscillator frequencies. These are board-specific */
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unsigned long at32_board_osc_rates[3] = {
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[0] = 32768, /* 32.768 kHz on RTC osc */
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[1] = 20000000, /* 20 MHz on osc0 */
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[2] = 12000000, /* 12 MHz on osc1 */
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};
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/*
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* The ATNGW100 mkII is very similar to the ATNGW100. Both have the AT32AP7000
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* chip on board; the difference is that the ATNGW100 mkII has 128 MB 32-bit
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* SDRAM (the ATNGW100 has 32 MB 16-bit SDRAM) and 256 MB 16-bit NAND flash
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* (the ATNGW100 has none.)
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*
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* The RAM difference is handled by the boot loader, so the only difference we
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* end up handling here is the NAND flash, EBI pin reservation and if LCDC or
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* MACB1 should be enabled.
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*/
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#ifdef CONFIG_BOARD_ATNGW100_MKII
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#include <linux/mtd/partitions.h>
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#include <mach/smc.h>
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static struct smc_timing nand_timing __initdata = {
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.ncs_read_setup = 0,
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.nrd_setup = 10,
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.ncs_write_setup = 0,
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.nwe_setup = 10,
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.ncs_read_pulse = 30,
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.nrd_pulse = 15,
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.ncs_write_pulse = 30,
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.nwe_pulse = 15,
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.read_cycle = 30,
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.write_cycle = 30,
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.ncs_read_recover = 0,
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.nrd_recover = 15,
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.ncs_write_recover = 0,
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/* WE# high -> RE# low min 60 ns */
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.nwe_recover = 50,
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};
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static struct smc_config nand_config __initdata = {
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.bus_width = 2,
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.nrd_controlled = 1,
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.nwe_controlled = 1,
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.nwait_mode = 0,
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.byte_write = 0,
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.tdf_cycles = 2,
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.tdf_mode = 0,
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};
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static struct mtd_partition nand_partitions[] = {
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{
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.name = "main",
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.offset = 0x00000000,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct atmel_nand_data atngw100mkii_nand_data __initdata = {
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.cle = 21,
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.ale = 22,
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.rdy_pin = GPIO_PIN_PB(28),
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.enable_pin = GPIO_PIN_PE(23),
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.bus_width_16 = true,
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.ecc_mode = NAND_ECC_SOFT,
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.parts = nand_partitions,
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.num_parts = ARRAY_SIZE(nand_partitions),
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};
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#endif
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/* Initialized by bootloader-specific startup code. */
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struct tag *bootloader_tags __initdata;
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struct eth_addr {
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u8 addr[6];
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};
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static struct eth_addr __initdata hw_addr[2];
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static struct macb_platform_data __initdata eth_data[2];
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static struct spi_board_info spi0_board_info[] __initdata = {
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{
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.modalias = "mtd_dataflash",
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.max_speed_hz = 8000000,
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.chip_select = 0,
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},
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};
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static struct mci_platform_data __initdata mci0_data = {
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.slot[0] = {
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.bus_width = 4,
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#if defined(CONFIG_BOARD_ATNGW100_MKII)
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.detect_pin = GPIO_PIN_PC(25),
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.wp_pin = GPIO_PIN_PE(22),
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#else
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.detect_pin = GPIO_PIN_PC(25),
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.wp_pin = GPIO_PIN_PE(0),
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#endif
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},
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};
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static struct usba_platform_data atngw100_usba_data __initdata = {
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#if defined(CONFIG_BOARD_ATNGW100_MKII)
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.vbus_pin = GPIO_PIN_PE(26),
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#else
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.vbus_pin = -ENODEV,
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#endif
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};
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/*
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* The next two functions should go away as the boot loader is
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* supposed to initialize the macb address registers with a valid
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* ethernet address. But we need to keep it around for a while until
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* we can be reasonably sure the boot loader does this.
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*
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* The phy_id is ignored as the driver will probe for it.
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*/
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static int __init parse_tag_ethernet(struct tag *tag)
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{
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int i;
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i = tag->u.ethernet.mac_index;
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if (i < ARRAY_SIZE(hw_addr))
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memcpy(hw_addr[i].addr, tag->u.ethernet.hw_address,
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sizeof(hw_addr[i].addr));
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return 0;
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}
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__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
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static void __init set_hw_addr(struct platform_device *pdev)
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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const u8 *addr;
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void __iomem *regs;
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struct clk *pclk;
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if (!res)
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return;
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if (pdev->id >= ARRAY_SIZE(hw_addr))
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return;
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addr = hw_addr[pdev->id].addr;
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if (!is_valid_ether_addr(addr))
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return;
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/*
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* Since this is board-specific code, we'll cheat and use the
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* physical address directly as we happen to know that it's
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* the same as the virtual address.
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*/
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regs = (void __iomem __force *)res->start;
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pclk = clk_get(&pdev->dev, "pclk");
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if (IS_ERR(pclk))
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return;
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clk_enable(pclk);
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__raw_writel((addr[3] << 24) | (addr[2] << 16)
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| (addr[1] << 8) | addr[0], regs + 0x98);
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__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
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clk_disable(pclk);
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clk_put(pclk);
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}
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void __init setup_board(void)
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{
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at32_map_usart(1, 0, 0); /* USART 1: /dev/ttyS0, DB9 */
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at32_setup_serial_console(0);
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}
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static const struct gpio_led ngw_leds[] = {
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{ .name = "sys", .gpio = GPIO_PIN_PA(16), .active_low = 1,
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.default_trigger = "heartbeat",
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},
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{ .name = "a", .gpio = GPIO_PIN_PA(19), .active_low = 1, },
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{ .name = "b", .gpio = GPIO_PIN_PE(19), .active_low = 1, },
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};
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static const struct gpio_led_platform_data ngw_led_data = {
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.num_leds = ARRAY_SIZE(ngw_leds),
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.leds = (void *) ngw_leds,
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};
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static struct platform_device ngw_gpio_leds = {
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.name = "leds-gpio",
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.id = -1,
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.dev = {
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.platform_data = (void *) &ngw_led_data,
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}
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};
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static struct i2c_gpio_platform_data i2c_gpio_data = {
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.sda_pin = GPIO_PIN_PA(6),
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.scl_pin = GPIO_PIN_PA(7),
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.sda_is_open_drain = 1,
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.scl_is_open_drain = 1,
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.udelay = 2, /* close to 100 kHz */
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};
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static struct platform_device i2c_gpio_device = {
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.name = "i2c-gpio",
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.id = 0,
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.dev = {
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.platform_data = &i2c_gpio_data,
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},
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};
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static struct i2c_board_info __initdata i2c_info[] = {
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/* NOTE: original ATtiny24 firmware is at address 0x0b */
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};
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static int __init atngw100_init(void)
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{
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unsigned i;
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/*
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* ATNGW100 mkII uses 32-bit SDRAM interface. Reserve the
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* SDRAM-specific pins so that nobody messes with them.
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*/
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#ifdef CONFIG_BOARD_ATNGW100_MKII
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at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
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smc_set_timing(&nand_config, &nand_timing);
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smc_set_configuration(3, &nand_config);
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at32_add_device_nand(0, &atngw100mkii_nand_data);
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#endif
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at32_add_device_usart(0);
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set_hw_addr(at32_add_device_eth(0, ð_data[0]));
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#ifndef CONFIG_BOARD_ATNGW100_MKII_LCD
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set_hw_addr(at32_add_device_eth(1, ð_data[1]));
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#endif
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at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
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at32_add_device_mci(0, &mci0_data);
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at32_add_device_usba(0, &atngw100_usba_data);
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for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
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at32_select_gpio(ngw_leds[i].gpio,
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AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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}
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platform_device_register(&ngw_gpio_leds);
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/* all these i2c/smbus pins should have external pullups for
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* open-drain sharing among all I2C devices. SDA and SCL do;
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* PB28/EXTINT3 (ATNGW100) and PE21 (ATNGW100 mkII) doesn't; it should
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* be SMBALERT# (for PMBus), but it's not available off-board.
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*/
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#ifdef CONFIG_BOARD_ATNGW100_MKII
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at32_select_periph(GPIO_PIOE_BASE, 1 << 21, 0, AT32_GPIOF_PULLUP);
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#else
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at32_select_periph(GPIO_PIOB_BASE, 1 << 28, 0, AT32_GPIOF_PULLUP);
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#endif
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at32_select_gpio(i2c_gpio_data.sda_pin,
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AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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at32_select_gpio(i2c_gpio_data.scl_pin,
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AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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platform_device_register(&i2c_gpio_device);
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i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));
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return 0;
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}
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postcore_initcall(atngw100_init);
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static int __init atngw100_arch_init(void)
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{
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/* PB30 (ATNGW100) and PE30 (ATNGW100 mkII) is the otherwise unused
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* jumper on the mainboard, with an external pullup; the jumper grounds
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* it. Use it however you like, including letting U-Boot or Linux tweak
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* boot sequences.
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*/
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#ifdef CONFIG_BOARD_ATNGW100_MKII
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at32_select_gpio(GPIO_PIN_PE(30), 0);
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gpio_request(GPIO_PIN_PE(30), "j15");
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gpio_direction_input(GPIO_PIN_PE(30));
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gpio_export(GPIO_PIN_PE(30), false);
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#else
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at32_select_gpio(GPIO_PIN_PB(30), 0);
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gpio_request(GPIO_PIN_PB(30), "j15");
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gpio_direction_input(GPIO_PIN_PB(30));
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gpio_export(GPIO_PIN_PB(30), false);
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#endif
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/* set_irq_type() after the arch_initcall for EIC has run, and
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* before the I2C subsystem could try using this IRQ.
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*/
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return irq_set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING);
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}
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arch_initcall(atngw100_arch_init);
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