840 lines
23 KiB
C
840 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
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#include "dpu_encoder_phys.h"
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#include "dpu_hw_interrupts.h"
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#include "dpu_core_irq.h"
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#include "dpu_formats.h"
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#include "dpu_trace.h"
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#define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
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(e) && (e)->base.parent ? \
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(e)->base.parent->base.id : -1, \
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(e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
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#define DPU_ERROR_CMDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
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(e) && (e)->base.parent ? \
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(e)->base.parent->base.id : -1, \
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(e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
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#define to_dpu_encoder_phys_cmd(x) \
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container_of(x, struct dpu_encoder_phys_cmd, base)
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#define PP_TIMEOUT_MAX_TRIALS 10
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/*
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* Tearcheck sync start and continue thresholds are empirically found
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* based on common panels In the future, may want to allow panels to override
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* these default values
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*/
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#define DEFAULT_TEARCHECK_SYNC_THRESH_START 4
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#define DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE 4
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#define DPU_ENC_WR_PTR_START_TIMEOUT_US 20000
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static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc)
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{
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return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false;
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}
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static bool dpu_encoder_phys_cmd_mode_fixup(
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struct dpu_encoder_phys *phys_enc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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if (phys_enc)
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DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n");
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return true;
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}
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static void _dpu_encoder_phys_cmd_update_intf_cfg(
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struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_encoder_phys_cmd *cmd_enc =
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to_dpu_encoder_phys_cmd(phys_enc);
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struct dpu_hw_ctl *ctl;
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struct dpu_hw_intf_cfg intf_cfg = { 0 };
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if (!phys_enc)
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return;
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ctl = phys_enc->hw_ctl;
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if (!ctl || !ctl->ops.setup_intf_cfg)
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return;
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intf_cfg.intf = phys_enc->intf_idx;
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intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
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intf_cfg.stream_sel = cmd_enc->stream_sel;
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intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
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ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
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}
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static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
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{
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struct dpu_encoder_phys *phys_enc = arg;
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unsigned long lock_flags;
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int new_cnt;
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u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
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if (!phys_enc || !phys_enc->hw_pp)
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return;
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DPU_ATRACE_BEGIN("pp_done_irq");
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/* notify all synchronous clients first, then asynchronous clients */
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if (phys_enc->parent_ops->handle_frame_done)
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phys_enc->parent_ops->handle_frame_done(phys_enc->parent,
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phys_enc, event);
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spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
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new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
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spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
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trace_dpu_enc_phys_cmd_pp_tx_done(DRMID(phys_enc->parent),
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phys_enc->hw_pp->idx - PINGPONG_0,
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new_cnt, event);
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/* Signal any waiting atomic commit thread */
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wake_up_all(&phys_enc->pending_kickoff_wq);
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DPU_ATRACE_END("pp_done_irq");
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}
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static void dpu_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx)
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{
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struct dpu_encoder_phys *phys_enc = arg;
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struct dpu_encoder_phys_cmd *cmd_enc;
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if (!phys_enc || !phys_enc->hw_pp)
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return;
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DPU_ATRACE_BEGIN("rd_ptr_irq");
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cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
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if (phys_enc->parent_ops->handle_vblank_virt)
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phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
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phys_enc);
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atomic_add_unless(&cmd_enc->pending_vblank_cnt, -1, 0);
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wake_up_all(&cmd_enc->pending_vblank_wq);
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DPU_ATRACE_END("rd_ptr_irq");
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}
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static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx)
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{
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struct dpu_encoder_phys *phys_enc = arg;
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struct dpu_encoder_phys_cmd *cmd_enc;
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if (!phys_enc || !phys_enc->hw_ctl)
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return;
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DPU_ATRACE_BEGIN("ctl_start_irq");
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cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
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atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0);
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/* Signal any waiting ctl start interrupt */
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wake_up_all(&phys_enc->pending_kickoff_wq);
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DPU_ATRACE_END("ctl_start_irq");
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}
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static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
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{
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struct dpu_encoder_phys *phys_enc = arg;
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if (!phys_enc)
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return;
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if (phys_enc->parent_ops->handle_underrun_virt)
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phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
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phys_enc);
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}
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static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
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struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_encoder_irq *irq;
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irq = &phys_enc->irq[INTR_IDX_CTL_START];
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irq->hw_idx = phys_enc->hw_ctl->idx;
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irq->irq_idx = -EINVAL;
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irq = &phys_enc->irq[INTR_IDX_PINGPONG];
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irq->hw_idx = phys_enc->hw_pp->idx;
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irq->irq_idx = -EINVAL;
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irq = &phys_enc->irq[INTR_IDX_RDPTR];
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irq->hw_idx = phys_enc->hw_pp->idx;
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irq->irq_idx = -EINVAL;
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irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
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irq->hw_idx = phys_enc->intf_idx;
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irq->irq_idx = -EINVAL;
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}
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static void dpu_encoder_phys_cmd_mode_set(
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struct dpu_encoder_phys *phys_enc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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struct dpu_encoder_phys_cmd *cmd_enc =
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to_dpu_encoder_phys_cmd(phys_enc);
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if (!phys_enc || !mode || !adj_mode) {
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DPU_ERROR("invalid args\n");
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return;
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}
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phys_enc->cached_mode = *adj_mode;
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DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
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drm_mode_debug_printmodeline(adj_mode);
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_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
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}
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static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
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struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_encoder_phys_cmd *cmd_enc =
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to_dpu_encoder_phys_cmd(phys_enc);
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u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
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bool do_log = false;
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if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl)
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return -EINVAL;
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cmd_enc->pp_timeout_report_cnt++;
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if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) {
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frame_event |= DPU_ENCODER_FRAME_EVENT_PANEL_DEAD;
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do_log = true;
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} else if (cmd_enc->pp_timeout_report_cnt == 1) {
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do_log = true;
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}
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trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent),
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phys_enc->hw_pp->idx - PINGPONG_0,
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cmd_enc->pp_timeout_report_cnt,
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atomic_read(&phys_enc->pending_kickoff_cnt),
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frame_event);
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/* to avoid flooding, only log first time, and "dead" time */
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if (do_log) {
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DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",
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DRMID(phys_enc->parent),
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phys_enc->hw_pp->idx - PINGPONG_0,
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phys_enc->hw_ctl->idx - CTL_0,
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cmd_enc->pp_timeout_report_cnt,
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atomic_read(&phys_enc->pending_kickoff_cnt));
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dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
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}
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atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
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/* request a ctl reset before the next kickoff */
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phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
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if (phys_enc->parent_ops->handle_frame_done)
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phys_enc->parent_ops->handle_frame_done(
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phys_enc->parent, phys_enc, frame_event);
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return -ETIMEDOUT;
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}
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static int _dpu_encoder_phys_cmd_wait_for_idle(
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struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_encoder_phys_cmd *cmd_enc =
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to_dpu_encoder_phys_cmd(phys_enc);
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struct dpu_encoder_wait_info wait_info;
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int ret;
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if (!phys_enc) {
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DPU_ERROR("invalid encoder\n");
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return -EINVAL;
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}
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wait_info.wq = &phys_enc->pending_kickoff_wq;
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wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
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wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
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ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_PINGPONG,
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&wait_info);
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if (ret == -ETIMEDOUT)
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_dpu_encoder_phys_cmd_handle_ppdone_timeout(phys_enc);
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else if (!ret)
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cmd_enc->pp_timeout_report_cnt = 0;
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return ret;
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}
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static int dpu_encoder_phys_cmd_control_vblank_irq(
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struct dpu_encoder_phys *phys_enc,
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bool enable)
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{
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int ret = 0;
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int refcount;
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if (!phys_enc || !phys_enc->hw_pp) {
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DPU_ERROR("invalid encoder\n");
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return -EINVAL;
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}
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refcount = atomic_read(&phys_enc->vblank_refcount);
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/* Slave encoders don't report vblank */
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if (!dpu_encoder_phys_cmd_is_master(phys_enc))
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goto end;
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/* protect against negative */
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if (!enable && refcount == 0) {
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ret = -EINVAL;
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goto end;
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}
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DRM_DEBUG_KMS("id:%u pp:%d enable=%s/%d\n", DRMID(phys_enc->parent),
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phys_enc->hw_pp->idx - PINGPONG_0,
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enable ? "true" : "false", refcount);
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if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
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ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_RDPTR);
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else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
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ret = dpu_encoder_helper_unregister_irq(phys_enc,
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INTR_IDX_RDPTR);
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end:
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if (ret) {
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DRM_ERROR("vblank irq err id:%u pp:%d ret:%d, enable %s/%d\n",
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DRMID(phys_enc->parent),
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phys_enc->hw_pp->idx - PINGPONG_0, ret,
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enable ? "true" : "false", refcount);
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}
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return ret;
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}
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static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
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bool enable)
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{
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struct dpu_encoder_phys_cmd *cmd_enc;
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if (!phys_enc)
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return;
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cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
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trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent),
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phys_enc->hw_pp->idx - PINGPONG_0,
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enable, atomic_read(&phys_enc->vblank_refcount));
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if (enable) {
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dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_PINGPONG);
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dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
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dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
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if (dpu_encoder_phys_cmd_is_master(phys_enc))
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dpu_encoder_helper_register_irq(phys_enc,
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INTR_IDX_CTL_START);
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} else {
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if (dpu_encoder_phys_cmd_is_master(phys_enc))
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dpu_encoder_helper_unregister_irq(phys_enc,
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INTR_IDX_CTL_START);
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dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
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dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
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dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_PINGPONG);
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}
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}
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static void dpu_encoder_phys_cmd_tearcheck_config(
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struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_encoder_phys_cmd *cmd_enc =
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to_dpu_encoder_phys_cmd(phys_enc);
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struct dpu_hw_tear_check tc_cfg = { 0 };
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struct drm_display_mode *mode;
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bool tc_enable = true;
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u32 vsync_hz;
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struct msm_drm_private *priv;
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struct dpu_kms *dpu_kms;
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if (!phys_enc || !phys_enc->hw_pp) {
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DPU_ERROR("invalid encoder\n");
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return;
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}
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mode = &phys_enc->cached_mode;
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DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
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if (!phys_enc->hw_pp->ops.setup_tearcheck ||
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!phys_enc->hw_pp->ops.enable_tearcheck) {
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DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
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return;
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}
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dpu_kms = phys_enc->dpu_kms;
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if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev_private) {
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DPU_ERROR("invalid device\n");
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return;
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}
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priv = dpu_kms->dev->dev_private;
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/*
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* TE default: dsi byte clock calculated base on 70 fps;
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* around 14 ms to complete a kickoff cycle if te disabled;
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* vclk_line base on 60 fps; write is faster than read;
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* init == start == rdptr;
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*
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* vsync_count is ratio of MDP VSYNC clock frequency to LCD panel
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* frequency divided by the no. of rows (lines) in the LCDpanel.
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*/
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vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync");
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if (vsync_hz <= 0) {
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DPU_DEBUG_CMDENC(cmd_enc, "invalid - vsync_hz %u\n",
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vsync_hz);
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return;
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}
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tc_cfg.vsync_count = vsync_hz /
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(mode->vtotal * drm_mode_vrefresh(mode));
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/* enable external TE after kickoff to avoid premature autorefresh */
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tc_cfg.hw_vsync_mode = 0;
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/*
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* By setting sync_cfg_height to near max register value, we essentially
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* disable dpu hw generated TE signal, since hw TE will arrive first.
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* Only caveat is if due to error, we hit wrap-around.
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*/
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tc_cfg.sync_cfg_height = 0xFFF0;
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tc_cfg.vsync_init_val = mode->vdisplay;
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tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START;
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tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE;
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tc_cfg.start_pos = mode->vdisplay;
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tc_cfg.rd_ptr_irq = mode->vdisplay + 1;
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DPU_DEBUG_CMDENC(cmd_enc,
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"tc %d vsync_clk_speed_hz %u vtotal %u vrefresh %u\n",
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phys_enc->hw_pp->idx - PINGPONG_0, vsync_hz,
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mode->vtotal, drm_mode_vrefresh(mode));
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DPU_DEBUG_CMDENC(cmd_enc,
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"tc %d enable %u start_pos %u rd_ptr_irq %u\n",
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phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos,
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tc_cfg.rd_ptr_irq);
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DPU_DEBUG_CMDENC(cmd_enc,
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"tc %d hw_vsync_mode %u vsync_count %u vsync_init_val %u\n",
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phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.hw_vsync_mode,
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tc_cfg.vsync_count, tc_cfg.vsync_init_val);
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DPU_DEBUG_CMDENC(cmd_enc,
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"tc %d cfgheight %u thresh_start %u thresh_cont %u\n",
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phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height,
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tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue);
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phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg);
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phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable);
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}
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static void _dpu_encoder_phys_cmd_pingpong_config(
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struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_encoder_phys_cmd *cmd_enc =
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to_dpu_encoder_phys_cmd(phys_enc);
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if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp
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|| !phys_enc->hw_ctl->ops.setup_intf_cfg) {
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DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != 0);
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return;
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}
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DPU_DEBUG_CMDENC(cmd_enc, "pp %d, enabling mode:\n",
|
|
phys_enc->hw_pp->idx - PINGPONG_0);
|
|
drm_mode_debug_printmodeline(&phys_enc->cached_mode);
|
|
|
|
_dpu_encoder_phys_cmd_update_intf_cfg(phys_enc);
|
|
dpu_encoder_phys_cmd_tearcheck_config(phys_enc);
|
|
}
|
|
|
|
static bool dpu_encoder_phys_cmd_needs_single_flush(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
/**
|
|
* we do separate flush for each CTL and let
|
|
* CTL_START synchronize them
|
|
*/
|
|
return false;
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_enable_helper(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct dpu_hw_ctl *ctl;
|
|
u32 flush_mask = 0;
|
|
|
|
if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp) {
|
|
DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
|
|
return;
|
|
}
|
|
|
|
dpu_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);
|
|
|
|
_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
|
|
|
|
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
|
|
return;
|
|
|
|
ctl = phys_enc->hw_ctl;
|
|
ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx);
|
|
ctl->ops.update_pending_flush(ctl, flush_mask);
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct dpu_encoder_phys_cmd *cmd_enc =
|
|
to_dpu_encoder_phys_cmd(phys_enc);
|
|
|
|
if (!phys_enc || !phys_enc->hw_pp) {
|
|
DPU_ERROR("invalid phys encoder\n");
|
|
return;
|
|
}
|
|
|
|
DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
|
|
|
|
if (phys_enc->enable_state == DPU_ENC_ENABLED) {
|
|
DPU_ERROR("already enabled\n");
|
|
return;
|
|
}
|
|
|
|
dpu_encoder_phys_cmd_enable_helper(phys_enc);
|
|
phys_enc->enable_state = DPU_ENC_ENABLED;
|
|
}
|
|
|
|
static void _dpu_encoder_phys_cmd_connect_te(
|
|
struct dpu_encoder_phys *phys_enc, bool enable)
|
|
{
|
|
if (!phys_enc || !phys_enc->hw_pp ||
|
|
!phys_enc->hw_pp->ops.connect_external_te)
|
|
return;
|
|
|
|
trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable);
|
|
phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable);
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_prepare_idle_pc(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
_dpu_encoder_phys_cmd_connect_te(phys_enc, false);
|
|
}
|
|
|
|
static int dpu_encoder_phys_cmd_get_line_count(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct dpu_hw_pingpong *hw_pp;
|
|
|
|
if (!phys_enc || !phys_enc->hw_pp)
|
|
return -EINVAL;
|
|
|
|
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
|
|
return -EINVAL;
|
|
|
|
hw_pp = phys_enc->hw_pp;
|
|
if (!hw_pp->ops.get_line_count)
|
|
return -EINVAL;
|
|
|
|
return hw_pp->ops.get_line_count(hw_pp);
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct dpu_encoder_phys_cmd *cmd_enc =
|
|
to_dpu_encoder_phys_cmd(phys_enc);
|
|
|
|
if (!phys_enc || !phys_enc->hw_pp) {
|
|
DPU_ERROR("invalid encoder\n");
|
|
return;
|
|
}
|
|
DRM_DEBUG_KMS("id:%u pp:%d state:%d\n", DRMID(phys_enc->parent),
|
|
phys_enc->hw_pp->idx - PINGPONG_0,
|
|
phys_enc->enable_state);
|
|
|
|
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
|
|
DPU_ERROR_CMDENC(cmd_enc, "already disabled\n");
|
|
return;
|
|
}
|
|
|
|
if (phys_enc->hw_pp->ops.enable_tearcheck)
|
|
phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false);
|
|
phys_enc->enable_state = DPU_ENC_DISABLED;
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct dpu_encoder_phys_cmd *cmd_enc =
|
|
to_dpu_encoder_phys_cmd(phys_enc);
|
|
|
|
if (!phys_enc) {
|
|
DPU_ERROR("invalid encoder\n");
|
|
return;
|
|
}
|
|
kfree(cmd_enc);
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_get_hw_resources(
|
|
struct dpu_encoder_phys *phys_enc,
|
|
struct dpu_encoder_hw_resources *hw_res)
|
|
{
|
|
hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_CMD;
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_prepare_for_kickoff(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct dpu_encoder_phys_cmd *cmd_enc =
|
|
to_dpu_encoder_phys_cmd(phys_enc);
|
|
int ret;
|
|
|
|
if (!phys_enc || !phys_enc->hw_pp) {
|
|
DPU_ERROR("invalid encoder\n");
|
|
return;
|
|
}
|
|
DRM_DEBUG_KMS("id:%u pp:%d pending_cnt:%d\n", DRMID(phys_enc->parent),
|
|
phys_enc->hw_pp->idx - PINGPONG_0,
|
|
atomic_read(&phys_enc->pending_kickoff_cnt));
|
|
|
|
/*
|
|
* Mark kickoff request as outstanding. If there are more than one,
|
|
* outstanding, then we have to wait for the previous one to complete
|
|
*/
|
|
ret = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc);
|
|
if (ret) {
|
|
/* force pending_kickoff_cnt 0 to discard failed kickoff */
|
|
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
|
|
DRM_ERROR("failed wait_for_idle: id:%u ret:%d pp:%d\n",
|
|
DRMID(phys_enc->parent), ret,
|
|
phys_enc->hw_pp->idx - PINGPONG_0);
|
|
}
|
|
|
|
DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n",
|
|
phys_enc->hw_pp->idx - PINGPONG_0,
|
|
atomic_read(&phys_enc->pending_kickoff_cnt));
|
|
}
|
|
|
|
static int _dpu_encoder_phys_cmd_wait_for_ctl_start(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct dpu_encoder_phys_cmd *cmd_enc =
|
|
to_dpu_encoder_phys_cmd(phys_enc);
|
|
struct dpu_encoder_wait_info wait_info;
|
|
int ret;
|
|
|
|
if (!phys_enc || !phys_enc->hw_ctl) {
|
|
DPU_ERROR("invalid argument(s)\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
wait_info.wq = &phys_enc->pending_kickoff_wq;
|
|
wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt;
|
|
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
|
|
|
|
ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_CTL_START,
|
|
&wait_info);
|
|
if (ret == -ETIMEDOUT) {
|
|
DPU_ERROR_CMDENC(cmd_enc, "ctl start interrupt wait failed\n");
|
|
ret = -EINVAL;
|
|
} else if (!ret)
|
|
ret = 0;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dpu_encoder_phys_cmd_wait_for_tx_complete(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
int rc;
|
|
struct dpu_encoder_phys_cmd *cmd_enc;
|
|
|
|
if (!phys_enc)
|
|
return -EINVAL;
|
|
|
|
cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
|
|
|
|
rc = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc);
|
|
if (rc) {
|
|
DRM_ERROR("failed wait_for_idle: id:%u ret:%d intf:%d\n",
|
|
DRMID(phys_enc->parent), rc,
|
|
phys_enc->intf_idx - INTF_0);
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int dpu_encoder_phys_cmd_wait_for_commit_done(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
int rc = 0;
|
|
struct dpu_encoder_phys_cmd *cmd_enc;
|
|
|
|
if (!phys_enc)
|
|
return -EINVAL;
|
|
|
|
cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
|
|
|
|
/* only required for master controller */
|
|
if (dpu_encoder_phys_cmd_is_master(phys_enc))
|
|
rc = _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc);
|
|
|
|
/* required for both controllers */
|
|
if (!rc && cmd_enc->serialize_wait4pp)
|
|
dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int dpu_encoder_phys_cmd_wait_for_vblank(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
int rc = 0;
|
|
struct dpu_encoder_phys_cmd *cmd_enc;
|
|
struct dpu_encoder_wait_info wait_info;
|
|
|
|
if (!phys_enc)
|
|
return -EINVAL;
|
|
|
|
cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
|
|
|
|
/* only required for master controller */
|
|
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
|
|
return rc;
|
|
|
|
wait_info.wq = &cmd_enc->pending_vblank_wq;
|
|
wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt;
|
|
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
|
|
|
|
atomic_inc(&cmd_enc->pending_vblank_cnt);
|
|
|
|
rc = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_RDPTR,
|
|
&wait_info);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_handle_post_kickoff(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
if (!phys_enc)
|
|
return;
|
|
|
|
/**
|
|
* re-enable external TE, either for the first time after enabling
|
|
* or if disabled for Autorefresh
|
|
*/
|
|
_dpu_encoder_phys_cmd_connect_te(phys_enc, true);
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_trigger_start(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
if (!phys_enc)
|
|
return;
|
|
|
|
dpu_encoder_helper_trigger_start(phys_enc);
|
|
}
|
|
|
|
static void dpu_encoder_phys_cmd_init_ops(
|
|
struct dpu_encoder_phys_ops *ops)
|
|
{
|
|
ops->is_master = dpu_encoder_phys_cmd_is_master;
|
|
ops->mode_set = dpu_encoder_phys_cmd_mode_set;
|
|
ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup;
|
|
ops->enable = dpu_encoder_phys_cmd_enable;
|
|
ops->disable = dpu_encoder_phys_cmd_disable;
|
|
ops->destroy = dpu_encoder_phys_cmd_destroy;
|
|
ops->get_hw_resources = dpu_encoder_phys_cmd_get_hw_resources;
|
|
ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq;
|
|
ops->wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done;
|
|
ops->prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff;
|
|
ops->wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete;
|
|
ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;
|
|
ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
|
|
ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
|
|
ops->irq_control = dpu_encoder_phys_cmd_irq_control;
|
|
ops->restore = dpu_encoder_phys_cmd_enable_helper;
|
|
ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
|
|
ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff;
|
|
ops->get_line_count = dpu_encoder_phys_cmd_get_line_count;
|
|
}
|
|
|
|
struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
|
|
struct dpu_enc_phys_init_params *p)
|
|
{
|
|
struct dpu_encoder_phys *phys_enc = NULL;
|
|
struct dpu_encoder_phys_cmd *cmd_enc = NULL;
|
|
struct dpu_encoder_irq *irq;
|
|
int i, ret = 0;
|
|
|
|
DPU_DEBUG("intf %d\n", p->intf_idx - INTF_0);
|
|
|
|
cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL);
|
|
if (!cmd_enc) {
|
|
ret = -ENOMEM;
|
|
DPU_ERROR("failed to allocate\n");
|
|
return ERR_PTR(ret);
|
|
}
|
|
phys_enc = &cmd_enc->base;
|
|
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
|
|
phys_enc->intf_idx = p->intf_idx;
|
|
|
|
dpu_encoder_phys_cmd_init_ops(&phys_enc->ops);
|
|
phys_enc->parent = p->parent;
|
|
phys_enc->parent_ops = p->parent_ops;
|
|
phys_enc->dpu_kms = p->dpu_kms;
|
|
phys_enc->split_role = p->split_role;
|
|
phys_enc->intf_mode = INTF_MODE_CMD;
|
|
phys_enc->enc_spinlock = p->enc_spinlock;
|
|
cmd_enc->stream_sel = 0;
|
|
phys_enc->enable_state = DPU_ENC_DISABLED;
|
|
for (i = 0; i < INTR_IDX_MAX; i++) {
|
|
irq = &phys_enc->irq[i];
|
|
INIT_LIST_HEAD(&irq->cb.list);
|
|
irq->irq_idx = -EINVAL;
|
|
irq->hw_idx = -EINVAL;
|
|
irq->cb.arg = phys_enc;
|
|
}
|
|
|
|
irq = &phys_enc->irq[INTR_IDX_CTL_START];
|
|
irq->name = "ctl_start";
|
|
irq->intr_type = DPU_IRQ_TYPE_CTL_START;
|
|
irq->intr_idx = INTR_IDX_CTL_START;
|
|
irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq;
|
|
|
|
irq = &phys_enc->irq[INTR_IDX_PINGPONG];
|
|
irq->name = "pp_done";
|
|
irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP;
|
|
irq->intr_idx = INTR_IDX_PINGPONG;
|
|
irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq;
|
|
|
|
irq = &phys_enc->irq[INTR_IDX_RDPTR];
|
|
irq->name = "pp_rd_ptr";
|
|
irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR;
|
|
irq->intr_idx = INTR_IDX_RDPTR;
|
|
irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq;
|
|
|
|
irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
|
|
irq->name = "underrun";
|
|
irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
|
|
irq->intr_idx = INTR_IDX_UNDERRUN;
|
|
irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;
|
|
|
|
atomic_set(&phys_enc->vblank_refcount, 0);
|
|
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
|
|
atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
|
|
atomic_set(&cmd_enc->pending_vblank_cnt, 0);
|
|
init_waitqueue_head(&phys_enc->pending_kickoff_wq);
|
|
init_waitqueue_head(&cmd_enc->pending_vblank_wq);
|
|
|
|
DPU_DEBUG_CMDENC(cmd_enc, "created\n");
|
|
|
|
return phys_enc;
|
|
|
|
return ERR_PTR(ret);
|
|
}
|