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ea09631536
The clock and reset bindings are going through different trees, and while the patch doesn't contain any value defined in that header, it still includes those files and result in a build breakage when building the DT without the matching clock and reset patches applied. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
145 lines
3.0 KiB
Plaintext
145 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
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/*
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* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
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* Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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clocks {
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osc24M: clk-24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk-32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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cpus {
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cpu {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram-controller@1c00000 {
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compatible = "allwinner,suniv-f1c100s-system-control",
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"allwinner,sun4i-a10-system-control";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_d: sram@10000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0 {
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compatible = "allwinner,suniv-f1c100s-sram-d",
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"allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,suniv-f1c100s-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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intc: interrupt-controller@1c20400 {
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compatible = "allwinner,suniv-f1c100s-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,suniv-f1c100s-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <38>, <39>, <40>;
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clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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uart0_pe_pins: uart0-pe-pins {
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pins = "PE0", "PE1";
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function = "uart0";
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};
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};
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timer@1c20c00 {
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compatible = "allwinner,suniv-f1c100s-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <13>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@1c20ca0 {
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compatible = "allwinner,suniv-f1c100s-wdt",
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"allwinner,sun4i-a10-wdt";
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reg = <0x01c20ca0 0x20>;
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};
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uart0: serial@1c25000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25000 0x400>;
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interrupts = <1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 38>;
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resets = <&ccu 24>;
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status = "disabled";
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};
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uart1: serial@1c25400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25400 0x400>;
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interrupts = <2>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 39>;
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resets = <&ccu 25>;
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status = "disabled";
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};
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uart2: serial@1c25800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25800 0x400>;
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interrupts = <3>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 40>;
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resets = <&ccu 26>;
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status = "disabled";
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};
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};
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};
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