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a4c902887f
[ Upstream commit 92025b90f18d45e26b7f17d68756b1abd771b9d3 ] The hardware codec on the A10, A10s, A13 and A20 needs buffer in the first 256MB of RAM. This was solved by setting the CMA pool at a fixed address in that range. However, in recent kernels there's something else that comes in and reserve some range that end up conflicting with our default pool requirement, and thus makes its reservation fail. The video codec will then use buffers from the usual default pool, outside of the range it can access, and will fail to decode anything. Since we're only concerned about that 256MB, we can however relax the allocation to just specify the range that's allowed, and not try to enforce a specific address. Fixes:5949bc5602("ARM: dts: sun4i-a10: Add Video Engine and reserved memory nodes") Fixes:9604320101("ARM: dts: sun5i: Add Video Engine and reserved memory nodes") Fixes:c2a641a748("ARM: dts: sun7i-a20: Add Video Engine and reserved memory nodes") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20200704130829.34297-1-maxime@cerno.tech Signed-off-by: Sasha Levin <sashal@kernel.org>
799 lines
19 KiB
Plaintext
799 lines
19 KiB
Plaintext
/*
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* Copyright 2012-2015 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/sun5i-ccu.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/reset/sun5i-ccu.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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clocks = <&ccu CLK_CPU>;
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};
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};
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer-lcd0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
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status = "disabled";
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};
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framebuffer-lcd0-tve0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-tve0";
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clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
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<&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
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status = "disabled";
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: clk-24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk-32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
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default-pool {
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compatible = "shared-dma-pool";
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size = <0x6000000>;
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alloc-ranges = <0x40000000 0x10000000>;
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reusable;
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linux,cma-default;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges;
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ranges;
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system-control@1c00000 {
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compatible = "allwinner,sun5i-a13-system-control";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_a: sram@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 0xc000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00000000 0xc000>;
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emac_sram: sram-section@8000 {
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compatible = "allwinner,sun5i-a13-sram-a3-a4",
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"allwinner,sun4i-a10-sram-a3-a4";
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reg = <0x8000 0x4000>;
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status = "disabled";
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};
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};
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sram_d: sram@10000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0 {
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compatible = "allwinner,sun5i-a13-sram-d",
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"allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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sram_c: sram@1d00000 {
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compatible = "mmio-sram";
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reg = <0x01d00000 0xd0000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x01d00000 0xd0000>;
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ve_sram: sram-section@0 {
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compatible = "allwinner,sun5i-a13-sram-c1",
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"allwinner,sun4i-a10-sram-c1";
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reg = <0x000000 0x80000>;
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};
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};
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};
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mbus: dram-controller@1c01000 {
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compatible = "allwinner,sun5i-a13-mbus";
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reg = <0x01c01000 0x1000>;
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clocks = <&ccu 99>;
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dma-ranges = <0x00000000 0x40000000 0x20000000>;
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#interconnect-cells = <1>;
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};
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dma: dma-controller@1c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <27>;
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clocks = <&ccu CLK_AHB_DMA>;
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#dma-cells = <2>;
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};
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nfc: nand-controller@1c03000 {
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compatible = "allwinner,sun4i-a10-nand";
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reg = <0x01c03000 0x1000>;
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interrupts = <37>;
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clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 3>;
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dma-names = "rxtx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi0: spi@1c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 27>,
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<&dma SUN4I_DMA_DEDICATED 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@1c06000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 9>,
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<&dma SUN4I_DMA_DEDICATED 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tve0: tv-encoder@1c0a000 {
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compatible = "allwinner,sun4i-a10-tv-encoder";
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reg = <0x01c0a000 0x1000>;
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clocks = <&ccu CLK_AHB_TVE>;
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resets = <&ccu RST_TVE>;
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status = "disabled";
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port {
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tve0_in_tcon0: endpoint {
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remote-endpoint = <&tcon0_out_tve0>;
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};
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};
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};
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emac: ethernet@1c0b000 {
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compatible = "allwinner,sun4i-a10-emac";
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reg = <0x01c0b000 0x1000>;
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interrupts = <55>;
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clocks = <&ccu CLK_AHB_EMAC>;
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allwinner,sram = <&emac_sram 1>;
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status = "disabled";
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};
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mdio: mdio@1c0b080 {
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compatible = "allwinner,sun4i-a10-mdio";
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reg = <0x01c0b080 0x14>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tcon0: lcd-controller@1c0c000 {
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compatible = "allwinner,sun5i-a13-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <44>;
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resets = <&ccu RST_LCD>;
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reset-names = "lcd";
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clocks = <&ccu CLK_AHB_LCD>,
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<&ccu CLK_TCON_CH0>,
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<&ccu CLK_TCON_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon-pixel-clock";
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#clock-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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reg = <0>;
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tcon0_in_be0: endpoint {
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remote-endpoint = <&be0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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tcon0_out_tve0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&tve0_in_tcon0>;
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allwinner,tcon-channel = <1>;
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};
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};
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun5i-a13-video-engine";
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reg = <0x01c0e000 0x1000>;
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clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
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<&ccu CLK_DRAM_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_VE>;
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interrupts = <53>;
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allwinner,sram = <&ve_sram 1>;
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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interrupts = <32>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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interrupts = <33>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@1c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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interrupts = <34>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@1c13000 {
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compatible = "allwinner,sun4i-a10-musb";
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reg = <0x01c13000 0x0400>;
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clocks = <&ccu CLK_AHB_OTG>;
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interrupts = <38>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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allwinner,sram = <&otg_sram 1>;
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dr_mode = "otg";
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status = "disabled";
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};
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usbphy: phy@1c13400 {
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#phy-cells = <1>;
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compatible = "allwinner,sun5i-a13-usb-phy";
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reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
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reg-names = "phy_ctrl", "pmu1";
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clocks = <&ccu CLK_USB_PHY0>;
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clock-names = "usb_phy";
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resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
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reset-names = "usb0_reset", "usb1_reset";
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status = "disabled";
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};
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ehci0: usb@1c14000 {
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compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
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reg = <0x01c14000 0x100>;
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interrupts = <39>;
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clocks = <&ccu CLK_AHB_EHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci0: usb@1c14400 {
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compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
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reg = <0x01c14400 0x100>;
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interrupts = <40>;
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clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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crypto: crypto-engine@1c15000 {
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compatible = "allwinner,sun5i-a13-crypto",
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"allwinner,sun4i-a10-crypto";
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reg = <0x01c15000 0x1000>;
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|
interrupts = <54>;
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|
clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
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clock-names = "ahb", "mod";
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};
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spi2: spi@1c17000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c17000 0x1000>;
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interrupts = <12>;
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clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 29>,
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<&dma SUN4I_DMA_DEDICATED 28>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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|
ccu: clock@1c20000 {
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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|
#clock-cells = <1>;
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#reset-cells = <1>;
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};
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|
intc: interrupt-controller@1c20400 {
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compatible = "allwinner,sun4i-a10-ic";
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|
reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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|
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|
pio: pinctrl@1c20800 {
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reg = <0x01c20800 0x400>;
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|
interrupts = <28>;
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|
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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emac_pd_pins: emac-pd-pins {
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pins = "PD6", "PD7", "PD10",
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"PD11", "PD12", "PD13", "PD14",
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"PD15", "PD18", "PD19", "PD20",
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"PD21", "PD22", "PD23", "PD24",
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"PD25", "PD26", "PD27";
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function = "emac";
|
|
};
|
|
|
|
i2c0_pins: i2c0-pins {
|
|
pins = "PB0", "PB1";
|
|
function = "i2c0";
|
|
};
|
|
|
|
i2c1_pins: i2c1-pins {
|
|
pins = "PB15", "PB16";
|
|
function = "i2c1";
|
|
};
|
|
|
|
i2c2_pins: i2c2-pins {
|
|
pins = "PB17", "PB18";
|
|
function = "i2c2";
|
|
};
|
|
|
|
ir0_rx_pin: ir0-rx-pin {
|
|
pins = "PB4";
|
|
function = "ir0";
|
|
};
|
|
|
|
lcd_rgb565_pins: lcd-rgb565-pins {
|
|
pins = "PD3", "PD4", "PD5", "PD6", "PD7",
|
|
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
|
|
"PD19", "PD20", "PD21", "PD22", "PD23",
|
|
"PD24", "PD25", "PD26", "PD27";
|
|
function = "lcd0";
|
|
};
|
|
|
|
lcd_rgb666_pins: lcd-rgb666-pins {
|
|
pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
|
|
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
|
|
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
|
|
"PD24", "PD25", "PD26", "PD27";
|
|
function = "lcd0";
|
|
};
|
|
|
|
mmc0_pins: mmc0-pins {
|
|
pins = "PF0", "PF1", "PF2", "PF3",
|
|
"PF4", "PF5";
|
|
function = "mmc0";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
|
|
pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11";
|
|
function = "mmc2";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
mmc2_8bit_pins: mmc2-8bit-pins {
|
|
pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11", "PC12", "PC13",
|
|
"PC14", "PC15";
|
|
function = "mmc2";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
nand_pins: nand-pins {
|
|
pins = "PC0", "PC1", "PC2",
|
|
"PC5", "PC8", "PC9", "PC10",
|
|
"PC11", "PC12", "PC13", "PC14",
|
|
"PC15";
|
|
function = "nand0";
|
|
};
|
|
|
|
nand_cs0_pin: nand-cs0-pin {
|
|
pins = "PC4";
|
|
function = "nand0";
|
|
};
|
|
|
|
nand_rb0_pin: nand-rb0-pin {
|
|
pins = "PC6";
|
|
function = "nand0";
|
|
};
|
|
|
|
pwm0_pin: pwm0-pin {
|
|
pins = "PB2";
|
|
function = "pwm";
|
|
};
|
|
|
|
spi2_pe_pins: spi2-pe-pins {
|
|
pins = "PE1", "PE2", "PE3";
|
|
function = "spi2";
|
|
};
|
|
|
|
spi2_cs0_pe_pin: spi2-cs0-pe-pin {
|
|
pins = "PE0";
|
|
function = "spi2";
|
|
};
|
|
|
|
uart1_pe_pins: uart1-pe-pins {
|
|
pins = "PE10", "PE11";
|
|
function = "uart1";
|
|
};
|
|
|
|
uart1_pg_pins: uart1-pg-pins {
|
|
pins = "PG3", "PG4";
|
|
function = "uart1";
|
|
};
|
|
|
|
uart2_pd_pins: uart2-pd-pins {
|
|
pins = "PD2", "PD3";
|
|
function = "uart2";
|
|
};
|
|
|
|
uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
|
|
pins = "PD4", "PD5";
|
|
function = "uart2";
|
|
};
|
|
|
|
uart3_pg_pins: uart3-pg-pins {
|
|
pins = "PG9", "PG10";
|
|
function = "uart3";
|
|
};
|
|
|
|
uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
|
|
pins = "PG11", "PG12";
|
|
function = "uart3";
|
|
};
|
|
};
|
|
|
|
timer@1c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0x90>;
|
|
interrupts = <22>,
|
|
<23>,
|
|
<24>,
|
|
<25>,
|
|
<67>,
|
|
<68>;
|
|
clocks = <&ccu CLK_HOSC>;
|
|
};
|
|
|
|
wdt: watchdog@1c20c90 {
|
|
compatible = "allwinner,sun4i-a10-wdt";
|
|
reg = <0x01c20c90 0x10>;
|
|
interrupts = <24>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
ir0: ir@1c21800 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <5>;
|
|
reg = <0x01c21800 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lradc: lradc@1c22800 {
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
reg = <0x01c22800 0x100>;
|
|
interrupts = <31>;
|
|
status = "disabled";
|
|
};
|
|
|
|
codec: codec@1c22c00 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-codec";
|
|
reg = <0x01c22c00 0x40>;
|
|
interrupts = <30>;
|
|
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
|
clock-names = "apb", "codec";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
|
<&dma SUN4I_DMA_NORMAL 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sid: eeprom@1c23800 {
|
|
compatible = "allwinner,sun4i-a10-sid";
|
|
reg = <0x01c23800 0x10>;
|
|
};
|
|
|
|
rtp: rtp@1c25000 {
|
|
compatible = "allwinner,sun5i-a13-ts";
|
|
reg = <0x01c25000 0x100>;
|
|
interrupts = <29>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
uart0: serial@1c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <1>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@1c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <2>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@1c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <3>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@1c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@1c2ac00 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <7>;
|
|
clocks = <&ccu CLK_APB1_I2C0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@1c2b000 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <8>;
|
|
clocks = <&ccu CLK_APB1_I2C1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@1c2b400 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <9>;
|
|
clocks = <&ccu CLK_APB1_I2C2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
timer@1c60000 {
|
|
compatible = "allwinner,sun5i-a13-hstimer";
|
|
reg = <0x01c60000 0x1000>;
|
|
interrupts = <82>, <83>;
|
|
clocks = <&ccu CLK_AHB_HSTIMER>;
|
|
};
|
|
|
|
fe0: display-frontend@1e00000 {
|
|
compatible = "allwinner,sun5i-a13-display-frontend";
|
|
reg = <0x01e00000 0x20000>;
|
|
interrupts = <47>;
|
|
clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
|
|
<&ccu CLK_DRAM_DE_FE>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_DE_FE>;
|
|
interconnects = <&mbus 19>;
|
|
interconnect-names = "dma-mem";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
fe0_out: port@1 {
|
|
reg = <1>;
|
|
|
|
fe0_out_be0: endpoint {
|
|
remote-endpoint = <&be0_in_fe0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
be0: display-backend@1e60000 {
|
|
compatible = "allwinner,sun5i-a13-display-backend";
|
|
reg = <0x01e60000 0x10000>;
|
|
interrupts = <47>;
|
|
clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
|
|
<&ccu CLK_DRAM_DE_BE>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_DE_BE>;
|
|
interconnects = <&mbus 18>;
|
|
interconnect-names = "dma-mem";
|
|
status = "disabled";
|
|
|
|
assigned-clocks = <&ccu CLK_DE_BE>;
|
|
assigned-clock-rates = <300000000>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
be0_in: port@0 {
|
|
reg = <0>;
|
|
|
|
be0_in_fe0: endpoint {
|
|
remote-endpoint = <&fe0_out_be0>;
|
|
};
|
|
};
|
|
|
|
be0_out: port@1 {
|
|
reg = <1>;
|
|
|
|
be0_out_tcon0: endpoint {
|
|
remote-endpoint = <&tcon0_in_be0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|