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fcaf20360a
Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
142 lines
3.3 KiB
Plaintext
142 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DTS file for SPEAr320 SoC
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*
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* Copyright 2012 Viresh Kumar <vireshk@kernel.org>
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*/
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/include/ "spear3xx.dtsi"
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/ {
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x40000000 0x40000000 0x80000000
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0xd0000000 0xd0000000 0x30000000>;
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pinmux: pinmux@b3000000 {
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compatible = "st,spear320-pinmux";
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reg = <0xb3000000 0x1000>;
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#gpio-range-cells = <3>;
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};
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clcd@90000000 {
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compatible = "arm,pl110", "arm,primecell";
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reg = <0x90000000 0x1000>;
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interrupts = <8>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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fsmc: flash@4c000000 {
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compatible = "st,spear600-fsmc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x4c000000 0x1000 /* FSMC Register */
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0x50000000 0x0010 /* NAND Base DATA */
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0x50020000 0x0010 /* NAND Base ADDR */
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0x50010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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status = "disabled";
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};
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sdhci@70000000 {
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compatible = "st,sdhci-spear";
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reg = <0x70000000 0x100>;
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interrupts = <10>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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shirq: interrupt-controller@0xb3000000 {
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compatible = "st,spear320-shirq";
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reg = <0xb3000000 0x1000>;
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interrupts = <30 28 29 1>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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spi1: spi@a5000000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0xa5000000 0x1000>;
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interrupts = <15>;
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interrupt-parent = <&shirq>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@a6000000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0xa6000000 0x1000>;
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interrupts = <16>;
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interrupt-parent = <&shirq>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pwm: pwm@a8000000 {
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compatible ="st,spear-pwm";
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reg = <0xa8000000 0x1000>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0xa0000000 0xa0000000 0x20000000
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0xd0000000 0xd0000000 0x30000000>;
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i2c1: i2c@a7000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xa7000000 0x1000>;
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interrupts = <21>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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serial@a3000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xa3000000 0x1000>;
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interrupts = <13>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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serial@a4000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xa4000000 0x1000>;
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interrupts = <14>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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gpiopinctrl: gpio@b3000000 {
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compatible = "st,spear-plgpio";
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reg = <0xb3000000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinmux 0 0 102>;
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status = "disabled";
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st-plgpio,ngpio = <102>;
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st-plgpio,enb-reg = <0x24>;
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st-plgpio,wdata-reg = <0x34>;
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st-plgpio,dir-reg = <0x44>;
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st-plgpio,ie-reg = <0x64>;
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st-plgpio,rdata-reg = <0x54>;
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st-plgpio,mis-reg = <0x84>;
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st-plgpio,eit-reg = <0x94>;
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};
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};
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};
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};
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