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10256a4755
With the Meson8m2 SoC the canvas module was moved from offset 0x20 (Meson8) to offset 0x48 (same as on Meson8b). The offsets inside the canvas module are identical. Correct the offset so the driver uses the correct registers. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
70 lines
1.5 KiB
Plaintext
70 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
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*/
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#include "meson8.dtsi"
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/ {
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model = "Amlogic Meson8m2 SoC";
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compatible = "amlogic,meson8m2";
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}; /* end of / */
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&clkc {
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compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
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};
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&dmcbus {
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/* the offset of the canvas registers has changed compared to Meson8 */
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/delete-node/ video-lut@20;
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canvas: video-lut@48 {
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compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
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reg = <0x48 0x14>;
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};
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};
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ðmac {
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compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
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reg = <0xc9410000 0x10000
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0xc1108140 0x8>;
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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resets = <&reset RESET_ETHERNET>;
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reset-names = "stmmaceth";
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};
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&pinctrl_aobus {
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compatible = "amlogic,meson8m2-aobus-pinctrl",
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"amlogic,meson8-aobus-pinctrl";
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};
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&pinctrl_cbus {
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compatible = "amlogic,meson8m2-cbus-pinctrl",
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"amlogic,meson8-cbus-pinctrl";
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eth_rgmii_pins: ethernet {
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mux {
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groups = "eth_tx_clk_50m", "eth_tx_en",
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"eth_txd3", "eth_txd2",
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"eth_txd1", "eth_txd0",
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"eth_rx_clk_in", "eth_rx_dv",
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"eth_rxd3", "eth_rxd2",
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"eth_rxd1", "eth_rxd0",
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"eth_mdio", "eth_mdc";
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function = "ethernet";
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bias-disable;
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};
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};
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};
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&saradc {
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compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
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};
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&wdt {
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compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
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};
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