1016 lines
24 KiB
Plaintext
1016 lines
24 KiB
Plaintext
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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*/
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/dts-v1/;
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#include "imx7d.dtsi"
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/ {
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model = "Freescale i.MX7D LPDDR3 12x12 Validation Board";
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compatible = "fsl,imx7d-12x12-lpddr3-val", "fsl,imx7d";
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 5000000 0>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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status = "okay";
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_gpio_keys>;
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pinctrl-1 = <&pinctrl_gpio_keys_sleep>;
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volume-up {
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label = "Volume Up";
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gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEUP>;
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};
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volume-down {
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label = "Volume Down";
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEDOWN>;
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};
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};
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pxp_v4l2_out {
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compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
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status = "okay";
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_aud_1v8: aud_1v8 {
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compatible = "regulator-fixed";
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regulator-name = "AUD_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_can1_3v3: can1-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "can1-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
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};
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reg_can2_3v3: can2-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "can2-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 11 GPIO_ACTIVE_LOW>;
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};
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reg_coedc_5v: coedc_5v {
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compatible = "regulator-fixed";
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regulator-name = "CODEC_5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_sd1_vmmc: sd1_vmmc{
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compatible = "regulator-fixed";
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regulator-name = "VCC_SD1";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_sd2_vmmc: sd2_vmmc{
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compatible = "regulator-fixed";
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regulator-name = "VCC_SD2";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg1_vbus: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg2_vbus: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "usb_otg2_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_vref_1v8: regulator@2 {
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compatible = "regulator-fixed";
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regulator-name = "vref-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
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compatible = "regulator-fixed";
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regulator-name = "mipi_dsi_pwr_on";
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gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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memory {
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reg = <0x80000000 0x80000000>;
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};
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};
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&adc1 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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&cpu0 {
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arm-supply = <&sw1a_reg>;
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};
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&epdc {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_epdc_0>;
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pinctrl-1 = <&pinctrl_epdc_0>;
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V3P3-supply = <&V3P3_reg>;
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VCOM-supply = <&VCOM_reg>;
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DISPLAY-supply = <&DISPLAY_reg>;
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status = "okay";
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};
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&epxp {
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status = "okay";
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};
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&ecspi1 {
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fsl,spi-num-chipselects = <1>;
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cs-gpios = <&gpio4 19 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
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pinctrl-1 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
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status = "disabled";
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spi_flash1: m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p32";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&fec1 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_enet1>;
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pinctrl-1 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <5>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_enet2>;
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pinctrl-1 = <&pinctrl_enet2>;
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pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
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assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "disabled";
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};
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&flexcan1 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_flexcan1>;
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pinctrl-1 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can1_3v3>;
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status = "disabled";
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};
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&flexcan2 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_flexcan2>;
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pinctrl-1 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can2_3v3>;
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status = "disabled";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_i2c1_1>;
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pinctrl-1 = <&pinctrl_i2c1_1>;
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status = "okay";
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pmic: pfuze3000@8 {
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compatible = "fsl,pfuze3000";
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reg = <0x8>;
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fsl,lpsr-mode;
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regulators {
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sw1a_reg: sw1a {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* use sw1c_reg to align with pfuze100/pfuze200 */
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sw1c_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen2_reg: vldo2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen3_reg: vccsd {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: v33 {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vldo3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vldo4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_i2c3_1>;
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pinctrl-1 = <&pinctrl_i2c3_1>;
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status = "okay";
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max7322: gpio@68 {
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compatible = "maxim,max7322";
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reg = <0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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max17135@48 {
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compatible = "maxim,max17135";
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reg = <0x48>;
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vneg_pwrup = <1>;
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gvee_pwrup = <2>;
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vpos_pwrup = <10>;
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gvdd_pwrup = <12>;
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gvdd_pwrdn = <1>;
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vpos_pwrdn = <2>;
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gvee_pwrdn = <8>;
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vneg_pwrdn = <10>;
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gpio_pmic_pwrgood = <&gpio2 31 0>;
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gpio_pmic_vcom_ctrl = <&gpio4 14 0>;
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gpio_pmic_wakeup = <&gpio4 23 0>;
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gpio_pmic_v3p3 = <&gpio4 20 0>;
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gpio_pmic_intr = <&gpio4 18 0>;
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regulators {
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DISPLAY_reg: DISPLAY {
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regulator-name = "DISPLAY";
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};
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GVDD_reg: GVDD {
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/* 20v */
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regulator-name = "GVDD";
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};
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GVEE_reg: GVEE {
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/* -22v */
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regulator-name = "GVEE";
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};
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HVINN_reg: HVINN {
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/* -22v */
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regulator-name = "HVINN";
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};
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HVINP_reg: HVINP {
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/* 20v */
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regulator-name = "HVINP";
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};
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VCOM_reg: VCOM {
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regulator-name = "VCOM";
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/* Real max value: -500000 */
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regulator-max-microvolt = <4325000>;
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/* Real min value: -4325000 */
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regulator-min-microvolt = <500000>;
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};
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VNEG_reg: VNEG {
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/* -15v */
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regulator-name = "VNEG";
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};
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VPOS_reg: VPOS {
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/* 15v */
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regulator-name = "VPOS";
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};
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V3P3_reg: V3P3 {
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regulator-name = "V3P3";
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};
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};
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};
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codec: wm8958@1a {
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compatible = "wlf,wm8958";
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reg = <0x1a>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>,
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<&clks IMX7D_CLK_DUMMY>;
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clock-names = "mclk1", "mclk2";
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DBVDD1-supply = <®_aud_1v8>;
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DBVDD2-supply = <®_aud_1v8>;
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DBVDD3-supply = <®_aud_1v8>;
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AVDD2-supply = <®_aud_1v8>;
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CPVDD-supply = <®_aud_1v8>;
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SPKVDD1-supply = <®_coedc_5v>;
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SPKVDD2-supply = <®_coedc_5v>;
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wlf,ldo1ena;
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wlf,ldo2ena;
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};
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};
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&iomuxc {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>;
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pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>;
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imx7d-12x12-lpddr3-arm2 {
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pinctrl_bt: btgrp-1 {
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fsl,pins = <
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MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* BT REG on */
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>;
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};
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pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
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fsl,pins = <
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MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2
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>;
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};
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pinctrl_ecspi1_1: ecspi1grp-1 {
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fsl,pins = <
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MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
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MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
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MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
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MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
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MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
|
|
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
|
|
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
|
|
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
|
|
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
|
|
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
|
|
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
|
|
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
|
|
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
|
|
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
|
|
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
|
|
>;
|
|
};
|
|
|
|
pinctrl_epdc_0: epdcgrp-0 {
|
|
fsl,pins = <
|
|
MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2
|
|
MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2
|
|
MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2
|
|
MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2
|
|
MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2
|
|
MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2
|
|
MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2
|
|
MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2
|
|
MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2
|
|
MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2
|
|
MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2
|
|
MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2
|
|
MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2
|
|
MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2
|
|
MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2
|
|
MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2
|
|
MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2
|
|
MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2
|
|
MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2
|
|
MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2
|
|
MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2
|
|
MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2
|
|
MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x2
|
|
MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x2
|
|
MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2
|
|
MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2
|
|
MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2
|
|
MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2
|
|
MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x2
|
|
MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x2
|
|
MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x80000000 /* pwr int */
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
|
|
MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
|
|
MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x59 /* STBY */
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
|
|
MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
|
|
MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x59 /* STBY */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_keys: gpio_keysgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
|
|
MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_keys_sleep: gpio_keysgrp_sleep {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14
|
|
MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14
|
|
>;
|
|
};
|
|
|
|
pinctrl_hog_1: hoggrp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000
|
|
MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000
|
|
MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x80000000
|
|
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x80000000
|
|
MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x80000000
|
|
MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000
|
|
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
|
|
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59
|
|
MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
|
|
MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
|
|
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
|
|
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_hog_mipi: hoggrp_mipi {
|
|
fsl,pins = <
|
|
MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
|
|
MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_hog_sd2_vselect: hoggrp_sd2vselect {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_hog_headphone_det: hoggrp_headphone_det {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1_1: i2c1grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
|
|
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_1: i2c2grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
|
|
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3_1: i2c3grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
|
|
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4_1: i2c4grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
|
|
MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif_dat: lcdifdatgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
|
|
MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
|
|
MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
|
|
MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
|
|
MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
|
|
MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
|
|
MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
|
|
MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
|
|
MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
|
|
MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
|
|
MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
|
|
MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
|
|
MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
|
|
MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
|
|
MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
|
|
MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
|
|
MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
|
|
MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
|
|
MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
|
|
MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
|
|
MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
|
|
MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
|
|
MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
|
|
MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_CLK__LCD_CLK 0x79
|
|
MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
|
|
MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
|
|
MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_mqs: mqsgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0
|
|
MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcie: pciegrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x2
|
|
MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x2
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai1: sai1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
|
|
MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
|
|
MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
|
|
MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f
|
|
MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
|
|
MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai2: sai2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
|
|
MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
|
|
MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
|
|
MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1_1: uart1grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
|
|
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3_1: uart3grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
|
|
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
|
|
MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
|
|
MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3dte_1: uart3dtegrp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
|
|
MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
|
|
MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79
|
|
MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_1: usdhc1grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_1: usdhc2grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_1: usdhc3grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_1_100mhz: usdhc3grp-1_100mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_1_200mhz: usdhc3grp-1_200mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
|
|
>;
|
|
};
|
|
|
|
pinctrl_sim1_1: sim1grp-1 {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x77
|
|
MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x77
|
|
MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x77
|
|
MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x73
|
|
MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x73
|
|
>;
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
&iomuxc_lpsr {
|
|
imx7d-12x12-lpddr3-arm2 {
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
|
|
>;
|
|
};
|
|
};
|
|
|
|
imx7d-sdb {
|
|
pinctrl_usbotg1_vbus: usbotg1vbusgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&lcdif {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pinctrl_lcdif_dat
|
|
&pinctrl_lcdif_ctrl>;
|
|
pinctrl-1 = <&pinctrl_lcdif_dat
|
|
&pinctrl_lcdif_ctrl>;
|
|
display = <&display0>;
|
|
status = "okay";
|
|
|
|
display0: display@0 {
|
|
bits-per-pixel = <16>;
|
|
bus-width = <24>;
|
|
|
|
display-timings {
|
|
native-mode = <&timing0>;
|
|
timing0: timing0 {
|
|
clock-frequency = <33500000>;
|
|
hactive = <800>;
|
|
vactive = <480>;
|
|
hback-porch = <89>;
|
|
hfront-porch = <164>;
|
|
vback-porch = <23>;
|
|
vfront-porch = <10>;
|
|
hsync-len = <10>;
|
|
vsync-len = <10>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&ocrams {
|
|
fsl,enable-lpsr;
|
|
};
|
|
|
|
&pcie {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcie>;
|
|
reset-gpio = <&gpio6 21 GPIO_ACTIVE_LOW>;
|
|
power-on-gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&sim1 {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pinctrl_sim1_1>;
|
|
pinctrl-1 = <&pinctrl_sim1_1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pinctrl_uart1_1>;
|
|
pinctrl-1 = <&pinctrl_uart1_1>;
|
|
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
|
|
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart3 {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pinctrl_uart3_1
|
|
&pinctrl_bt>;
|
|
pinctrl-1 = <&pinctrl_uart3_1
|
|
&pinctrl_bt>;
|
|
fsl,uart-has-rtscts;
|
|
assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
|
|
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
|
status = "okay";
|
|
/* for DTE mode, add below change */
|
|
/* fsl,dte-mode;*/
|
|
/* pinctrl-0 = <&pinctrl_uart3dte_1>; */
|
|
};
|
|
|
|
&usbotg1 {
|
|
vbus-supply = <®_usb_otg1_vbus>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
|
|
srp-disable;
|
|
hnp-disable;
|
|
adp-disable;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg2 {
|
|
vbus-supply = <®_usb_otg2_vbus>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usbotg2_vbus>;
|
|
srp-disable;
|
|
hnp-disable;
|
|
adp-disable;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pinctrl_usdhc1_1>;
|
|
pinctrl-1 = <&pinctrl_usdhc1_1>;
|
|
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
|
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
|
|
no-1-8-v;
|
|
keep-power-in-suspend;
|
|
enable-sdio-wakeup;
|
|
vmmc-supply = <®_sd1_vmmc>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
|
pinctrl-0 = <&pinctrl_usdhc2_1>;
|
|
pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
|
|
pinctrl-3 = <&pinctrl_usdhc2_1>;
|
|
cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
|
|
wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
|
|
keep-power-in-suspend;
|
|
enable-sdio-wakeup;
|
|
vmmc-supply = <®_sd2_vmmc>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
|
pinctrl-0 = <&pinctrl_usdhc3_1>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
|
|
pinctrl-3 = <&pinctrl_usdhc3_1>;
|
|
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
|
|
assigned-clock-rates = <400000000>;
|
|
bus-width = <8>;
|
|
auto-cmd23-broken;
|
|
non-removable;
|
|
keep-power-in-suspend;
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
};
|