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Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
85 lines
1.9 KiB
Plaintext
85 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2012 Armadeus Systems - <support@armadeus.com>
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* Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
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*
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* Based on mx51-babbage.dts
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*/
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/dts-v1/;
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#include "imx51.dtsi"
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/ {
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model = "Armadeus Systems APF51 module";
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compatible = "armadeus,imx51-apf51", "fsl,imx51";
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memory@90000000 {
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device_type = "memory";
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reg = <0x90000000 0x20000000>;
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};
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clocks {
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osc {
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clock-frequency = <33554432>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "mii";
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phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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status = "okay";
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};
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&iomuxc {
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imx51-apf51 {
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
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MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
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MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
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MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
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MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
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MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
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MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
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MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
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MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
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MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
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MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
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MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
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MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
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MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
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MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
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MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
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MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
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MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
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MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
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>;
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};
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};
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};
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&nfc {
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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