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fcaf20360a
Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
136 lines
2.4 KiB
Plaintext
136 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*/
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/dts-v1/;
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#include "imx1.dtsi"
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/ {
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model = "Freescale MX1 ADS";
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compatible = "fsl,imx1ads", "fsl,imx1";
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chosen {
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stdout-path = &uart1;
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};
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memory@8000000 {
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device_type = "memory";
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reg = <0x08000000 0x04000000>;
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};
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};
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&cspi1 {
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pinctrl-0 = <&pinctrl_cspi1>;
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cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&i2c {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c>;
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status = "okay";
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extgpio0: pcf8575@22 {
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compatible = "nxp,pcf8575";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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extgpio1: pcf8575@24 {
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compatible = "nxp,pcf8575";
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reg = <0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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status = "okay";
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};
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&weim {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_weim>;
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status = "okay";
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nor: nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0x00000000 0x02000000>;
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bank-width = <4>;
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fsl,weim-cs-timing = <0x00003e00 0x00000801>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&iomuxc {
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imx1-ads {
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pinctrl_cspi1: cspi1grp {
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fsl,pins = <
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MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
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MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
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MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
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MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
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MX1_PAD_SPI1_SS__GPIO3_15 0x0
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>;
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};
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pinctrl_i2c: i2cgrp {
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fsl,pins = <
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MX1_PAD_I2C_SCL__I2C_SCL 0x0
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MX1_PAD_I2C_SDA__I2C_SDA 0x0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX1_PAD_UART1_TXD__UART1_TXD 0x0
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MX1_PAD_UART1_RXD__UART1_RXD 0x0
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MX1_PAD_UART1_CTS__UART1_CTS 0x0
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MX1_PAD_UART1_RTS__UART1_RTS 0x0
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX1_PAD_UART2_TXD__UART2_TXD 0x0
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MX1_PAD_UART2_RXD__UART2_RXD 0x0
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MX1_PAD_UART2_CTS__UART2_CTS 0x0
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MX1_PAD_UART2_RTS__UART2_RTS 0x0
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>;
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};
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pinctrl_weim: weimgrp {
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fsl,pins = <
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MX1_PAD_A0__A0 0x0
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MX1_PAD_A16__A16 0x0
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MX1_PAD_A17__A17 0x0
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MX1_PAD_A18__A18 0x0
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MX1_PAD_A19__A19 0x0
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MX1_PAD_A20__A20 0x0
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MX1_PAD_A21__A21 0x0
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MX1_PAD_A22__A22 0x0
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MX1_PAD_A23__A23 0x0
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MX1_PAD_A24__A24 0x0
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MX1_PAD_BCLK__BCLK 0x0
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MX1_PAD_CS4__CS4 0x0
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MX1_PAD_DTACK__DTACK 0x0
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MX1_PAD_ECB__ECB 0x0
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MX1_PAD_LBA__LBA 0x0
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>;
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};
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};
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};
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