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47f28b41df
The PMU module of Mali400 GPU is optional and it looks that it is not
present on Exynos4210, because any access to its registers causes external
abort. This patch removes "pmu" interrupt for Exynos4210 SoCs, so the
driver will skip the PMU module. This fixes following fault during kernel
boot:
Unhandled fault: imprecise external abort (0x1406) at 0x00000000
(lima_pmu_init) from [<c059e6f8>] (lima_device_init+0x244/0x5a0)
(lima_device_init) from [<c059e40c>] (lima_pdev_probe+0x7c/0xd8)
(lima_pdev_probe) from [<c05afcb8>] (platform_drv_probe+0x48/0x9c)
(platform_drv_probe) from [<c05ad594>] (really_probe+0x1c4/0x400)
(really_probe) from [<c05ad988>] (driver_probe_device+0x78/0x1b8)
(driver_probe_device) from [<c05add30>] (device_driver_attach+0x58/0x60)
(device_driver_attach) from [<c05ade34>] (__driver_attach+0xfc/0x160)
(__driver_attach) from [<c05ab650>] (bus_for_each_dev+0x68/0xb4)
(bus_for_each_dev) from [<c05ac734>] (bus_add_driver+0x104/0x20c)
(bus_add_driver) from [<c05aece0>] (driver_register+0x78/0x10c)
(driver_register) from [<c0103214>] (do_one_initcall+0x8c/0x430)
(do_one_initcall) from [<c0f01328>] (kernel_init_freeable+0x3c8/0x4d0)
(kernel_init_freeable) from [<c0ac3aa0>] (kernel_init+0x8/0x10c)
(kernel_init) from [<c01010b4>] (ret_from_fork+0x14/0x20)
The PMU module seems to work fine on Exynos4412 SoCs, so the patch also
moves the interrupt definitions to exynos4210.dtsi and exynos4412.dtsi
respectively, to keep only the common part in exynos4.dtsi.
Fixes: 13efd80aca ("ARM: dts: exynos: Add GPU/Mali 400 node to Exynos4")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
812 lines
20 KiB
Plaintext
812 lines
20 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's Exynos4412 SoC device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
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* based board files can include this file and provide values for board specfic
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
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* nodes can be added to this file.
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*/
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#include "exynos4.dtsi"
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#include "exynos4-cpu-thermal.dtsi"
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/ {
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compatible = "samsung,exynos4412", "samsung,exynos4";
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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fimc-lite0 = &fimc_lite_0;
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fimc-lite1 = &fimc_lite_1;
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mshc0 = &mshc_0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@a00 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xA00>;
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clocks = <&clock CLK_ARM_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu1: cpu@a01 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xA01>;
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clocks = <&clock CLK_ARM_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu2: cpu@a02 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xA02>;
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clocks = <&clock CLK_ARM_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu3: cpu@a03 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xA03>;
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clocks = <&clock CLK_ARM_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <900000>;
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clock-latency-ns = <200000>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <900000>;
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clock-latency-ns = <200000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <925000>;
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clock-latency-ns = <200000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <950000>;
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clock-latency-ns = <200000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <975000>;
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clock-latency-ns = <200000>;
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};
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opp-700000000 {
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opp-hz = /bits/ 64 <700000000>;
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opp-microvolt = <987500>;
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clock-latency-ns = <200000>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <200000>;
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opp-suspend;
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};
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <1037500>;
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clock-latency-ns = <200000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1087500>;
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clock-latency-ns = <200000>;
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};
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opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <1137500>;
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clock-latency-ns = <200000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1187500>;
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clock-latency-ns = <200000>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1250000>;
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clock-latency-ns = <200000>;
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};
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opp-1400000000 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-microvolt = <1287500>;
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clock-latency-ns = <200000>;
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};
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cpu0_opp_1500: opp-1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <1350000>;
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clock-latency-ns = <200000>;
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turbo-mode;
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};
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};
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soc: soc {
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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wakup_eint: wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl_2: pinctrl@3860000 {
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <10 0>;
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};
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pinctrl_3: pinctrl@106e0000 {
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x106E0000 0x1000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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};
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sysram@2020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x40000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@2f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x2f000 0x1000>;
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};
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};
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pd_isp: isp-power-domain@10023ca0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CA0 0x20>;
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#power-domain-cells = <0>;
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label = "ISP";
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};
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l2c: l2-cache-controller@10502000 {
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compatible = "arm,pl310-cache";
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reg = <0x10502000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,tag-latency = <2 2 1>;
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arm,data-latency = <3 2 1>;
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arm,double-linefill = <1>;
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arm,double-linefill-incr = <0>;
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arm,double-linefill-wrap = <1>;
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arm,prefetch-drop = <1>;
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arm,prefetch-offset = <7>;
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};
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4412-clock";
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reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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};
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isp_clock: clock-controller@10048000 {
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compatible = "samsung,exynos4412-isp-clock";
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reg = <0x10048000 0x1000>;
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#clock-cells = <1>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_ACLK200>,
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<&clock CLK_ACLK400_MCUISP>;
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clock-names = "aclk200", "aclk400_mcuisp";
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};
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mct@10050000 {
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compatible = "samsung,exynos4412-mct";
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reg = <0x10050000 0x800>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map =
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<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
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<1 &combiner 12 5>,
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<2 &combiner 12 6>,
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<3 &combiner 12 7>,
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<4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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watchdog: watchdog@10060000 {
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compatible = "samsung,exynos5250-wdt";
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reg = <0x10060000 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_WDT>;
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clock-names = "watchdog";
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samsung,syscon-phandle = <&pmu_system_controller>;
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};
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adc: adc@126c0000 {
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compatible = "samsung,exynos4212-adc";
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reg = <0x126C0000 0x100>;
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interrupt-parent = <&combiner>;
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interrupts = <10 3>;
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clocks = <&clock CLK_TSADC>;
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clock-names = "adc";
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#io-channel-cells = <1>;
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io-channel-ranges;
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samsung,syscon-phandle = <&pmu_system_controller>;
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status = "disabled";
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};
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g2d: g2d@10800000 {
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compatible = "samsung,exynos4212-g2d";
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reg = <0x10800000 0x1000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
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clock-names = "sclk_fimg2d", "fimg2d";
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iommus = <&sysmmu_g2d>;
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};
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mshc_0: mmc@12550000 {
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compatible = "samsung,exynos4412-dw-mshc";
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reg = <0x12550000 0x1000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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fifo-depth = <0x80>;
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clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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sysmmu_g2d: sysmmu@10a40000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x10A40000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <4 7>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_isp: sysmmu@12260000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12260000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 2>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu";
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clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_drc: sysmmu@12270000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12270000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 3>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu";
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clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_fd: sysmmu@122a0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x122A0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 4>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu";
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clocks = <&isp_clock CLK_ISP_SMMU_FD>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_mcuctl: sysmmu@122b0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x122B0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 5>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu";
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clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_lite0: sysmmu@123b0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x123B0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 0>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu", "master";
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clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
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<&isp_clock CLK_ISP_FIMC_LITE0>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_lite1: sysmmu@123c0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x123C0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 1>;
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power-domains = <&pd_isp>;
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clock-names = "sysmmu", "master";
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clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
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<&isp_clock CLK_ISP_FIMC_LITE1>;
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#iommu-cells = <0>;
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};
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bus_dmc: bus_dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_acp: bus_acp {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_ACP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_acp_opp_table>;
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status = "disabled";
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};
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bus_c2c: bus_c2c {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_C2C>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_dmc_opp_table: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <900000>;
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};
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opp-134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <900000>;
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};
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <900000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <950000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1050000>;
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opp-suspend;
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};
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};
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bus_acp_opp_table: opp_table2 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
|
|
};
|
|
opp-134000000 {
|
|
opp-hz = /bits/ 64 <134000000>;
|
|
};
|
|
opp-160000000 {
|
|
opp-hz = /bits/ 64 <160000000>;
|
|
};
|
|
opp-267000000 {
|
|
opp-hz = /bits/ 64 <267000000>;
|
|
};
|
|
};
|
|
|
|
bus_leftbus: bus_leftbus {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DIV_GDL>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_leftbus_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_rightbus: bus_rightbus {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DIV_GDR>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_leftbus_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_display: bus_display {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_ACLK160>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_display_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_fsys: bus_fsys {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_ACLK133>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_fsys_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_peri: bus_peri {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_ACLK100>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_peri_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_mfc: bus_mfc {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_SCLK_MFC>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_leftbus_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_leftbus_opp_table: opp_table3 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-microvolt = <900000>;
|
|
};
|
|
opp-134000000 {
|
|
opp-hz = /bits/ 64 <134000000>;
|
|
opp-microvolt = <925000>;
|
|
};
|
|
opp-160000000 {
|
|
opp-hz = /bits/ 64 <160000000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp-200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
opp-microvolt = <1000000>;
|
|
opp-suspend;
|
|
};
|
|
};
|
|
|
|
bus_display_opp_table: opp_table4 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-160000000 {
|
|
opp-hz = /bits/ 64 <160000000>;
|
|
};
|
|
opp-200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
};
|
|
|
|
bus_fsys_opp_table: opp_table5 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
};
|
|
opp-134000000 {
|
|
opp-hz = /bits/ 64 <134000000>;
|
|
};
|
|
};
|
|
|
|
bus_peri_opp_table: opp_table6 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-50000000 {
|
|
opp-hz = /bits/ 64 <50000000>;
|
|
};
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&combiner {
|
|
samsung,combiner-nr = <20>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&camera {
|
|
clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
|
|
<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
|
|
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
|
|
|
|
/* fimc_[0-3] are configured outside, under phandles */
|
|
fimc_lite_0: fimc-lite@12390000 {
|
|
compatible = "samsung,exynos4212-fimc-lite";
|
|
reg = <0x12390000 0x1000>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&pd_isp>;
|
|
clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
|
|
clock-names = "flite";
|
|
iommus = <&sysmmu_fimc_lite0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fimc_lite_1: fimc-lite@123a0000 {
|
|
compatible = "samsung,exynos4212-fimc-lite";
|
|
reg = <0x123A0000 0x1000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&pd_isp>;
|
|
clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
|
|
clock-names = "flite";
|
|
iommus = <&sysmmu_fimc_lite1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fimc_is: fimc-is@12000000 {
|
|
compatible = "samsung,exynos4212-fimc-is";
|
|
reg = <0x12000000 0x260000>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&pd_isp>;
|
|
clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
|
|
<&isp_clock CLK_ISP_FIMC_LITE1>,
|
|
<&isp_clock CLK_ISP_PPMUISPX>,
|
|
<&isp_clock CLK_ISP_PPMUISPMX>,
|
|
<&isp_clock CLK_ISP_FIMC_ISP>,
|
|
<&isp_clock CLK_ISP_FIMC_DRC>,
|
|
<&isp_clock CLK_ISP_FIMC_FD>,
|
|
<&isp_clock CLK_ISP_MCUISP>,
|
|
<&isp_clock CLK_ISP_GICISP>,
|
|
<&isp_clock CLK_ISP_MCUCTL_ISP>,
|
|
<&isp_clock CLK_ISP_PWM_ISP>,
|
|
<&isp_clock CLK_ISP_DIV_ISP0>,
|
|
<&isp_clock CLK_ISP_DIV_ISP1>,
|
|
<&isp_clock CLK_ISP_DIV_MCUISP0>,
|
|
<&isp_clock CLK_ISP_DIV_MCUISP1>,
|
|
<&clock CLK_MOUT_MPLL_USER_T>,
|
|
<&clock CLK_ACLK200>,
|
|
<&clock CLK_ACLK400_MCUISP>,
|
|
<&clock CLK_DIV_ACLK200>,
|
|
<&clock CLK_DIV_ACLK400_MCUISP>,
|
|
<&clock CLK_UART_ISP_SCLK>;
|
|
clock-names = "lite0", "lite1", "ppmuispx",
|
|
"ppmuispmx", "isp",
|
|
"drc", "fd", "mcuisp",
|
|
"gicisp", "mcuctl_isp", "pwm_isp",
|
|
"ispdiv0", "ispdiv1", "mcuispdiv0",
|
|
"mcuispdiv1", "mpll", "aclk200",
|
|
"aclk400mcuisp", "div_aclk200",
|
|
"div_aclk400mcuisp", "uart";
|
|
iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
|
|
<&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
|
|
iommu-names = "isp", "drc", "fd", "mcuctl";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
pmu@10020000 {
|
|
reg = <0x10020000 0x3000>;
|
|
};
|
|
|
|
i2c1_isp: i2c-isp@12140000 {
|
|
compatible = "samsung,exynos4212-i2c-isp";
|
|
reg = <0x12140000 0x100>;
|
|
clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
|
|
clock-names = "i2c_isp";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&exynos_usbphy {
|
|
compatible = "samsung,exynos4x12-usb2-phy";
|
|
samsung,sysreg-phandle = <&sys_reg>;
|
|
};
|
|
|
|
&fimc_0 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
&fimc_1 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
&fimc_2 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,lcd-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
&fimc_3 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <1920 8192 1366 1920>;
|
|
samsung,rotators = <0>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,lcd-wb;
|
|
};
|
|
|
|
&gic {
|
|
cpu-offset = <0x4000>;
|
|
};
|
|
|
|
&gpu {
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gp",
|
|
"gpmmu",
|
|
"pp0",
|
|
"ppmmu0",
|
|
"pp1",
|
|
"ppmmu1",
|
|
"pp2",
|
|
"ppmmu2",
|
|
"pp3",
|
|
"ppmmu3",
|
|
"pmu";
|
|
operating-points-v2 = <&gpu_opp_table>;
|
|
|
|
gpu_opp_table: opp_table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-160000000 {
|
|
opp-hz = /bits/ 64 <160000000>;
|
|
opp-microvolt = <875000>;
|
|
};
|
|
opp-267000000 {
|
|
opp-hz = /bits/ 64 <267000000>;
|
|
opp-microvolt = <900000>;
|
|
};
|
|
opp-350000000 {
|
|
opp-hz = /bits/ 64 <350000000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp-440000000 {
|
|
opp-hz = /bits/ 64 <440000000>;
|
|
opp-microvolt = <1025000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&hdmi {
|
|
compatible = "samsung,exynos4212-hdmi";
|
|
};
|
|
|
|
&jpeg_codec {
|
|
compatible = "samsung,exynos4212-jpeg";
|
|
};
|
|
|
|
&rotator {
|
|
compatible = "samsung,exynos4212-rotator";
|
|
};
|
|
|
|
&mixer {
|
|
compatible = "samsung,exynos4212-mixer";
|
|
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
|
|
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
|
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
|
|
};
|
|
|
|
&pmu {
|
|
interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
|
|
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pmu_system_controller {
|
|
compatible = "samsung,exynos4412-pmu", "syscon";
|
|
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
|
"clkout4", "clkout8", "clkout9";
|
|
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
|
|
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
|
|
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
&tmu {
|
|
compatible = "samsung,exynos4412-tmu";
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 4>;
|
|
reg = <0x100C0000 0x100>;
|
|
clocks = <&clock 383>;
|
|
clock-names = "tmu_apbif";
|
|
status = "disabled";
|
|
};
|
|
|
|
#include "exynos4412-pinctrl.dtsi"
|