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https://github.com/brain-hackers/linux-brain.git
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6f3710f1f6
Accessing the NOR flash memory from the kernel will disrupt CPU sleep/ idles states and CPU hotplugging. We need to disable this DT node by default. Setups that want to access the flash can modify this entry to enable the flash again but also ensuring to disable CPU idle states and CPU hotplug. The platform firmware assumes the flash is always in read mode while Linux kernel driver leaves NOR flash in "read id" mode after initialization. If it gets used actively, it can be in some other state. So far we had not seen this issue as the NOR flash drivers in kernel were not enabled by default. However it was enable in multi_v7 config by Commit5f068190cc("ARM: multi_v7_defconfig: Enable support for CFI NOR FLASH") So, let's mark the NOR flash disabled so that the platform can boot again. This based on: Commit980bbff018("ARM64: juno: disable NOR flash node by default") Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
692 lines
15 KiB
Plaintext
692 lines
15 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Versatile Express
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*
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* CoreTile Express A15x2 A7x3
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* Cortex-A15_A7 MPCore (V2P-CA15_A7)
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*
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* HBI-0249A
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*/
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/dts-v1/;
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#include "vexpress-v2m-rs1.dtsi"
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/ {
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model = "V2P-CA15_CA7";
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arm,hbi = <0x249>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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i2c0 = &v2m_i2c_dvi;
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i2c1 = &v2m_i2c_pcie;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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cci-control-port = <&cci_control1>;
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cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <990>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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cci-control-port = <&cci_control1>;
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cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <990>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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cci-control-port = <&cci_control2>;
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cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
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capacity-dmips-mhz = <516>;
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dynamic-power-coefficient = <133>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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cci-control-port = <&cci_control2>;
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cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
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capacity-dmips-mhz = <516>;
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dynamic-power-coefficient = <133>;
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};
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cpu4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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cci-control-port = <&cci_control2>;
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cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
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capacity-dmips-mhz = <516>;
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dynamic-power-coefficient = <133>;
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};
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idle-states {
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CLUSTER_SLEEP_BIG: cluster-sleep-big {
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compatible = "arm,idle-state";
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local-timer-stop;
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2000>;
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};
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CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
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compatible = "arm,idle-state";
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local-timer-stop;
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entry-latency-us = <1000>;
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exit-latency-us = <500>;
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min-residency-us = <2500>;
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0x40000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Chipselect 2 is physically at 0x18000000 */
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vram: vram@18000000 {
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/* 8 MB of designated video RAM */
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compatible = "shared-dma-pool";
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reg = <0 0x18000000 0 0x00800000>;
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no-map;
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};
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};
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wdt@2a490000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0 0x2a490000 0 0x1000>;
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interrupts = <0 98 4>;
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clocks = <&oscclk6a>, <&oscclk6a>;
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clock-names = "wdogclk", "apb_pclk";
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};
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hdlcd@2b000000 {
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compatible = "arm,hdlcd";
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reg = <0 0x2b000000 0 0x1000>;
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interrupts = <0 85 4>;
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clocks = <&hdlcd_clk>;
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clock-names = "pxlclk";
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};
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memory-controller@2b0a0000 {
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compatible = "arm,pl341", "arm,primecell";
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reg = <0 0x2b0a0000 0 0x1000>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x2000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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cci@2c090000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0 0x2c090000 0 0x1000>;
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ranges = <0x0 0x0 0x2c090000 0x10000>;
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cci_control1: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control2: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r0";
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reg = <0x9000 0x5000>;
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interrupts = <0 105 4>,
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<0 101 4>,
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<0 102 4>,
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<0 103 4>,
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<0 104 4>;
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};
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};
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memory-controller@7ffd0000 {
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compatible = "arm,pl354", "arm,primecell";
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reg = <0 0x7ffd0000 0 0x1000>;
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interrupts = <0 86 4>,
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<0 87 4>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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};
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dma@7ff00000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0 0x7ff00000 0 0x1000>;
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interrupts = <0 92 4>,
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<0 88 4>,
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<0 89 4>,
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<0 90 4>,
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<0 91 4>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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};
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scc@7fff0000 {
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compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
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reg = <0 0x7fff0000 0 0x1000>;
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interrupts = <0 95 4>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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pmu-a15 {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <0 68 4>,
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<0 69 4>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>;
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};
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pmu-a7 {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <0 128 4>,
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<0 129 4>,
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<0 130 4>;
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interrupt-affinity = <&cpu2>,
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<&cpu3>,
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<&cpu4>;
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};
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oscclk6a: oscclk6a {
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/* Reference 24MHz clock */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "oscclk6a";
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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oscclk0 {
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/* A15 PLL 0 reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <17000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk0";
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};
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oscclk1 {
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/* A15 PLL 1 reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 1>;
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freq-range = <17000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk1";
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};
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oscclk2 {
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/* A7 PLL 0 reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <17000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk2";
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};
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oscclk3 {
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/* A7 PLL 1 reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 3>;
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freq-range = <17000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk3";
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};
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oscclk4 {
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/* External AXI master clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 4>;
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freq-range = <20000000 40000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk4";
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};
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hdlcd_clk: oscclk5 {
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/* HDLCD PLL reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 5>;
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freq-range = <23750000 165000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk5";
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};
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smbclk: oscclk6 {
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/* Static memory controller clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 6>;
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freq-range = <20000000 40000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk6";
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};
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oscclk7 {
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/* SYS PLL reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 7>;
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freq-range = <17000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk7";
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};
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oscclk8 {
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/* DDR2 PLL reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 8>;
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freq-range = <20000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk8";
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};
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volt-a15 {
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/* A15 CPU core voltage */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 0>;
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regulator-name = "A15 Vcore";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1050000>;
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regulator-always-on;
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label = "A15 Vcore";
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};
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volt-a7 {
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/* A7 CPU core voltage */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 1>;
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regulator-name = "A7 Vcore";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1050000>;
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regulator-always-on;
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label = "A7 Vcore";
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};
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amp-a15 {
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/* Total current for the two A15 cores */
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compatible = "arm,vexpress-amp";
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arm,vexpress-sysreg,func = <3 0>;
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label = "A15 Icore";
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};
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amp-a7 {
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/* Total current for the three A7 cores */
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compatible = "arm,vexpress-amp";
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arm,vexpress-sysreg,func = <3 1>;
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label = "A7 Icore";
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};
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temp-dcc {
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/* DCC internal temperature */
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compatible = "arm,vexpress-temp";
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arm,vexpress-sysreg,func = <4 0>;
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label = "DCC";
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};
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power-a15 {
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/* Total power for the two A15 cores */
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compatible = "arm,vexpress-power";
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arm,vexpress-sysreg,func = <12 0>;
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label = "A15 Pcore";
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};
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power-a7 {
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/* Total power for the three A7 cores */
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compatible = "arm,vexpress-power";
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arm,vexpress-sysreg,func = <12 1>;
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label = "A7 Pcore";
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};
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energy-a15 {
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/* Total energy for the two A15 cores */
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compatible = "arm,vexpress-energy";
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arm,vexpress-sysreg,func = <13 0>, <13 1>;
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label = "A15 Jcore";
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};
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energy-a7 {
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/* Total energy for the three A7 cores */
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compatible = "arm,vexpress-energy";
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arm,vexpress-sysreg,func = <13 2>, <13 3>;
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label = "A7 Jcore";
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};
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};
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etb@20010000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0x20010000 0 0x1000>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etb_in_port: endpoint {
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remote-endpoint = <&replicator_out_port0>;
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};
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};
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};
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};
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tpiu@20030000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0 0x20030000 0 0x1000>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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tpiu_in_port: endpoint {
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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};
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replicator {
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/* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-static-replicator";
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&etb_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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};
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in-ports {
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port {
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replicator_in_port0: endpoint {
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remote-endpoint = <&funnel_out_port0>;
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};
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};
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};
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};
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funnel@20040000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0x20040000 0 0x1000>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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funnel_out_port0: endpoint {
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remote-endpoint =
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<&replicator_in_port0>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel_in_port0: endpoint {
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remote-endpoint = <&ptm0_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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funnel_in_port1: endpoint {
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remote-endpoint = <&ptm1_out_port>;
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};
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};
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port@2 {
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reg = <2>;
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funnel_in_port2: endpoint {
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remote-endpoint = <&etm0_out_port>;
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};
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};
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/* Input port #3 is for ITM, not supported here */
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port@4 {
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reg = <4>;
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funnel_in_port4: endpoint {
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remote-endpoint = <&etm1_out_port>;
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};
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};
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port@5 {
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reg = <5>;
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funnel_in_port5: endpoint {
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remote-endpoint = <&etm2_out_port>;
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};
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};
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};
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};
|
|
|
|
ptm@2201c000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0x2201c000 0 0x1000>;
|
|
|
|
cpu = <&cpu0>;
|
|
clocks = <&oscclk6a>;
|
|
clock-names = "apb_pclk";
|
|
out-ports {
|
|
port {
|
|
ptm0_out_port: endpoint {
|
|
remote-endpoint = <&funnel_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@2201d000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0x2201d000 0 0x1000>;
|
|
|
|
cpu = <&cpu1>;
|
|
clocks = <&oscclk6a>;
|
|
clock-names = "apb_pclk";
|
|
out-ports {
|
|
port {
|
|
ptm1_out_port: endpoint {
|
|
remote-endpoint = <&funnel_in_port1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@2203c000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0x2203c000 0 0x1000>;
|
|
|
|
cpu = <&cpu2>;
|
|
clocks = <&oscclk6a>;
|
|
clock-names = "apb_pclk";
|
|
out-ports {
|
|
port {
|
|
etm0_out_port: endpoint {
|
|
remote-endpoint = <&funnel_in_port2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@2203d000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0x2203d000 0 0x1000>;
|
|
|
|
cpu = <&cpu3>;
|
|
clocks = <&oscclk6a>;
|
|
clock-names = "apb_pclk";
|
|
out-ports {
|
|
port {
|
|
etm1_out_port: endpoint {
|
|
remote-endpoint = <&funnel_in_port4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@2203e000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0x2203e000 0 0x1000>;
|
|
|
|
cpu = <&cpu4>;
|
|
clocks = <&oscclk6a>;
|
|
clock-names = "apb_pclk";
|
|
out-ports {
|
|
port {
|
|
etm2_out_port: endpoint {
|
|
remote-endpoint = <&funnel_in_port5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
smb: smb@8000000 {
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0x08000000 0x04000000>,
|
|
<1 0 0 0x14000000 0x04000000>,
|
|
<2 0 0 0x18000000 0x04000000>,
|
|
<3 0 0 0x1c000000 0x04000000>,
|
|
<4 0 0 0x0c000000 0x04000000>,
|
|
<5 0 0 0x10000000 0x04000000>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 63>;
|
|
interrupt-map = <0 0 0 &gic 0 0 4>,
|
|
<0 0 1 &gic 0 1 4>,
|
|
<0 0 2 &gic 0 2 4>,
|
|
<0 0 3 &gic 0 3 4>,
|
|
<0 0 4 &gic 0 4 4>,
|
|
<0 0 5 &gic 0 5 4>,
|
|
<0 0 6 &gic 0 6 4>,
|
|
<0 0 7 &gic 0 7 4>,
|
|
<0 0 8 &gic 0 8 4>,
|
|
<0 0 9 &gic 0 9 4>,
|
|
<0 0 10 &gic 0 10 4>,
|
|
<0 0 11 &gic 0 11 4>,
|
|
<0 0 12 &gic 0 12 4>,
|
|
<0 0 13 &gic 0 13 4>,
|
|
<0 0 14 &gic 0 14 4>,
|
|
<0 0 15 &gic 0 15 4>,
|
|
<0 0 16 &gic 0 16 4>,
|
|
<0 0 17 &gic 0 17 4>,
|
|
<0 0 18 &gic 0 18 4>,
|
|
<0 0 19 &gic 0 19 4>,
|
|
<0 0 20 &gic 0 20 4>,
|
|
<0 0 21 &gic 0 21 4>,
|
|
<0 0 22 &gic 0 22 4>,
|
|
<0 0 23 &gic 0 23 4>,
|
|
<0 0 24 &gic 0 24 4>,
|
|
<0 0 25 &gic 0 25 4>,
|
|
<0 0 26 &gic 0 26 4>,
|
|
<0 0 27 &gic 0 27 4>,
|
|
<0 0 28 &gic 0 28 4>,
|
|
<0 0 29 &gic 0 29 4>,
|
|
<0 0 30 &gic 0 30 4>,
|
|
<0 0 31 &gic 0 31 4>,
|
|
<0 0 32 &gic 0 32 4>,
|
|
<0 0 33 &gic 0 33 4>,
|
|
<0 0 34 &gic 0 34 4>,
|
|
<0 0 35 &gic 0 35 4>,
|
|
<0 0 36 &gic 0 36 4>,
|
|
<0 0 37 &gic 0 37 4>,
|
|
<0 0 38 &gic 0 38 4>,
|
|
<0 0 39 &gic 0 39 4>,
|
|
<0 0 40 &gic 0 40 4>,
|
|
<0 0 41 &gic 0 41 4>,
|
|
<0 0 42 &gic 0 42 4>;
|
|
};
|
|
|
|
site2: hsb@40000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0x40000000 0x3fef0000>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 3>;
|
|
interrupt-map = <0 0 &gic 0 36 4>,
|
|
<0 1 &gic 0 37 4>,
|
|
<0 2 &gic 0 38 4>,
|
|
<0 3 &gic 0 39 4>;
|
|
};
|
|
};
|
|
|
|
&nor_flash {
|
|
/*
|
|
* Unfortunately, accessing the flash disturbs the CPU idle states
|
|
* (suspend) and CPU hotplug of this platform. For this reason, flash
|
|
* hardware access is disabled by default on this platform alone.
|
|
*/
|
|
status = "disabled";
|
|
};
|