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6b381a8e2c
veyron jaq, jerry, minnie and speedy have mostly redundant regulator and pinctrl configurations for the panel/backlight. Consolidate these pieces in the eDP .dtsi. Also change the default power supply for the panel to 'panel_regulator', instead of overriding it in all the board files. pinky is the only device that uses 'vcc33_lcd' (the prior default), so overwrite it in this case. pinky doesn't have a complete display configuration, to keep things as they were delete the common nodes that didn't exist previously in pinky's board file. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
329 lines
5.7 KiB
Plaintext
329 lines
5.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Jaq Rev 1+ board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron-chromebook.dtsi"
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#include "cros-ec-sbs.dtsi"
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/ {
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model = "Google Jaq";
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compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
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"google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
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"google,veyron-jaq-rev1", "google,veyron-jaq",
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"google,veyron", "rockchip,rk3288";
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};
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&backlight {
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/* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
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brightness-levels = <
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0
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
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dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
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<&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
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regulators {
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mic_vcc: LDO_REG2 {
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regulator-name = "mic_vcc";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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};
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&sdmmc {
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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&sdmmc_bus4>;
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};
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&vcc_5v {
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enable-active-high;
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gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&drv_5v>;
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc50_hdmi_en>;
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};
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&gpio0 {
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gpio-line-names = "PMIC_SLEEP_AP",
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"DDRIO_PWROFF",
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"DDRIO_RETEN",
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"TS3A227E_INT_L",
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"PMIC_INT_L",
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"PWR_KEY_L",
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"AP_LID_INT_L",
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"EC_IN_RW",
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"AC_PRESENT_AP",
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/*
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* RECOVERY_SW_L is Chrome OS ABI. Schematics call
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* it REC_MODE_L.
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*/
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"RECOVERY_SW_L",
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"OTP_OUT",
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"HOST1_PWR_EN",
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"USBOTG_PWREN_H",
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"AP_WARM_RESET_H",
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"nFALUT2",
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"I2C0_SDA_PMIC",
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"I2C0_SCL_PMIC",
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"SUSPEND_L",
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"USB_INT";
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};
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&gpio2 {
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gpio-line-names = "CONFIG0",
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"CONFIG1",
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"CONFIG2",
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"",
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"",
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"",
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"",
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"CONFIG3",
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"",
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"EMMC_RST_L",
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"",
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"",
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"BL_PWR_EN",
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"AVDD_1V8_DISP_EN";
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};
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&gpio3 {
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gpio-line-names = "FLASH0_D0",
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"FLASH0_D1",
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"FLASH0_D2",
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"FLASH0_D3",
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"FLASH0_D4",
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"FLASH0_D5",
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"FLASH0_D6",
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"FLASH0_D7",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"FLASH0_CS2/EMMC_CMD",
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"",
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"FLASH0_DQS/EMMC_CLKO";
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};
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&gpio4 {
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gpio-line-names = "",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"UART0_RXD",
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"UART0_TXD",
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"UART0_CTS",
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"UART0_RTS",
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"SDIO0_D0",
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"SDIO0_D1",
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"SDIO0_D2",
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"SDIO0_D3",
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"SDIO0_CMD",
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"SDIO0_CLK",
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"BT_DEV_WAKE", /* Maybe missing from mighty? */
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"",
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"WIFI_ENABLE_H",
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"BT_ENABLE_L",
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"WIFI_HOST_WAKE",
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"BT_HOST_WAKE";
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};
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&gpio5 {
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gpio-line-names = "",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"SPI0_CLK",
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"SPI0_CS0",
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"SPI0_TXD",
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"SPI0_RXD",
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"",
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"",
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"",
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"VCC50_HDMI_EN";
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};
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&gpio6 {
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gpio-line-names = "I2S0_SCLK",
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"I2S0_LRCK_RX",
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"I2S0_LRCK_TX",
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"I2S0_SDI",
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"I2S0_SDO0",
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"HP_DET_H",
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"ALS_INT",
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"INT_CODEC",
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"I2S0_CLK",
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"I2C2_SDA",
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"I2C2_SCL",
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"MICDET",
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"",
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"",
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"",
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"",
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"SDMMC_D0",
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"SDMMC_D1",
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"SDMMC_D2",
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"SDMMC_D3",
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"SDMMC_CLK",
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"SDMMC_CMD";
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};
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&gpio7 {
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gpio-line-names = "LCDC_BL",
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"PWM_LOG",
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"BL_EN",
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"TRACKPAD_INT",
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"TPM_INT_H",
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"SDMMC_DET_L",
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/*
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* AP_FLASH_WP_L is Chrome OS ABI. Schematics call
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* it FW_WP_AP.
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*/
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"AP_FLASH_WP_L",
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"EC_INT",
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"CPU_NMI",
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"DVSOK",
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"SDMMC_WP", /* mighty only */
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"EDP_HPD",
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"DVS1",
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"nFALUT1", /* nFAULT1 on jaq */
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"LCD_EN",
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"DVS2",
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"VCC5V_GOOD_H",
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"I2C4_SDA_TP",
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"I2C4_SCL_TP",
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"I2C5_SDA_HDMI",
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"I2C5_SCL_HDMI",
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"5V_DRV",
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"UART2_RXD",
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"UART2_TXD";
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};
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&gpio8 {
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gpio-line-names = "RAM_ID0",
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"RAM_ID1",
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"RAM_ID2",
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"RAM_ID3",
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"I2C1_SDA_TPM",
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"I2C1_SCL_TPM",
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"SPI2_CLK",
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"SPI2_CS0",
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"SPI2_RXD",
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"SPI2_TXD";
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};
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&pinctrl {
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buck-5v {
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drv_5v: drv-5v {
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rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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hdmi {
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vcc50_hdmi_en: vcc50-hdmi-en {
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rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pmic {
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dvs_1: dvs-1 {
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rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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dvs_2: dvs-2 {
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rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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