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https://github.com/brain-hackers/linux-brain.git
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07f08d9cee
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
103 lines
2.1 KiB
Plaintext
103 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Brain Rev 0 board device tree source
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*
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* Copyright 2014 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron.dtsi"
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/ {
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model = "Google Brain";
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compatible = "google,veyron-brain-rev0", "google,veyron-brain",
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"google,veyron", "rockchip,rk3288";
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vcc33_sys: vcc33-sys {
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vin-supply = <&vcc_5v>;
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};
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vcc33_io: vcc33_io {
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compatible = "regulator-fixed";
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regulator-name = "vcc33_io";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc33_sys>;
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/* This is gated by vcc_18 too */
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};
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/* This turns on vbus for host2 and otg (dwc2) */
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vcc5_host2: vcc5-host2-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&usb2_pwr_en>;
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regulator-name = "vcc5_host2";
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&pinctrl {
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hdmi {
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vcc50_hdmi_en: vcc50-hdmi-en {
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rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pmic {
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dvs_1: dvs-1 {
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rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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dvs_2: dvs-2 {
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rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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usb-host {
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usb2_pwr_en: usb2-pwr-en {
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rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
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dvs-gpios = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>,
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<&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
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/delete-property/ vcc6-supply;
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regulators {
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/* vcc33_io is sourced directly from vcc33_sys */
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/delete-node/ LDO_REG1;
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/* This is not a pwren anymore, but the real power supply */
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vdd10_lcd: LDO_REG7 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-name = "vdd10_lcd";
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regulator-suspend-mem-disabled;
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};
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vcc18_hdmi: SWITCH_REG2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vcc18_hdmi";
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regulator-suspend-mem-disabled;
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};
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};
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc50_hdmi_en>;
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};
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