linux-brain/arch/arm/boot/dts/nspire.dtsi
Linus Walleij da5fbcb1d0 ARM: dts: Update the NSPIRE DTS files for DRM
The DRM subsystem graphics drivers require more granular
definition of the connection between display drivers and
panels, and a proper panel compatible. This utilizes the
bindings merged to the DRM subsystem to properly define
the display on the NSPIRE devices.

We also do away with the undocumented DT binding
"lcd-type".

We add both the clocks to the CLCD block so the driver
have full control over its clocking.

Link: https://lore.kernel.org/r/20190810074230.6492-1-linus.walleij@linaro.org
Cc: Daniel Tang <dt.tangr@gmail.com>
Cc: Fabian Vogt <fabian@ritter-vogt.de>
Tested-by: Fabian Vogt <fabian@ritter-vogt.de>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-13 15:28:34 +02:00

200 lines
3.5 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/boot/nspire.dtsi
*
* Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
cpus {
cpu@0 {
compatible = "arm,arm926ej-s";
};
};
bootrom: bootrom@0 {
reg = <0x00000000 0x80000>;
};
sram: sram@A4000000 {
device = "memory";
reg = <0xA4000000 0x20000>;
};
timer_clk: timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
base_clk: base_clk {
#clock-cells = <0>;
reg = <0x900B0024 0x4>;
};
ahb_clk: ahb_clk {
#clock-cells = <0>;
reg = <0x900B0024 0x4>;
clocks = <&base_clk>;
};
apb_pclk: apb_pclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clock-mult = <1>;
clocks = <&ahb_clk>;
};
usb_phy: usb_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
vbus_reg: vbus_reg {
compatible = "regulator-fixed";
regulator-name = "USB VBUS output";
regulator-type = "voltage";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
spi: spi@A9000000 {
reg = <0xA9000000 0x1000>;
};
usb0: usb@B0000000 {
compatible = "lsi,zevio-usb";
reg = <0xB0000000 0x1000>;
interrupts = <8>;
usb-phy = <&usb_phy>;
vbus-supply = <&vbus_reg>;
};
usb1: usb@B4000000 {
reg = <0xB4000000 0x1000>;
interrupts = <9>;
status = "disabled";
};
lcd: lcd@C0000000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0xC0000000 0x1000>;
interrupts = <21>;
/*
* We assume the same clock is fed to APB and CLCDCLK.
* There is some code to scale the clock down by a factor
* 48 for the display so likely the frequency to the
* display is 1MHz and the CLCDCLK is 48 MHz.
*/
clocks = <&apb_pclk>, <&apb_pclk>;
clock-names = "clcdclk", "apb_pclk";
};
adc: adc@C4000000 {
reg = <0xC4000000 0x1000>;
interrupts = <11>;
};
tdes: crypto@C8010000 {
reg = <0xC8010000 0x1000>;
};
sha256: crypto@CC000000 {
reg = <0xCC000000 0x1000>;
};
apb@90000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
clock-ranges;
ranges;
gpio: gpio@90000000 {
compatible = "lsi,zevio-gpio";
reg = <0x90000000 0x1000>;
interrupts = <7>;
gpio-controller;
#gpio-cells = <2>;
};
fast_timer: timer@90010000 {
reg = <0x90010000 0x1000>;
interrupts = <17>;
};
uart: serial@90020000 {
reg = <0x90020000 0x1000>;
interrupts = <1>;
};
timer0: timer@900C0000 {
reg = <0x900C0000 0x1000>;
clocks = <&timer_clk>;
};
timer1: timer@900D0000 {
reg = <0x900D0000 0x1000>;
interrupts = <19>;
clocks = <&timer_clk>;
};
watchdog: watchdog@90060000 {
compatible = "arm,amba-primecell";
reg = <0x90060000 0x1000>;
interrupts = <3>;
};
rtc: rtc@90090000 {
reg = <0x90090000 0x1000>;
interrupts = <4>;
};
misc: misc@900A0000 {
reg = <0x900A0000 0x1000>;
};
pwr: pwr@900B0000 {
reg = <0x900B0000 0x1000>;
interrupts = <15>;
};
keypad: input@900E0000 {
compatible = "ti,nspire-keypad";
reg = <0x900E0000 0x1000>;
interrupts = <16>;
scan-interval = <1000>;
row-delay = <200>;
clocks = <&apb_pclk>;
};
contrast: contrast@900F0000 {
reg = <0x900F0000 0x1000>;
};
led: led@90110000 {
reg = <0x90110000 0x1000>;
};
};
};
};