808 lines
18 KiB
Plaintext
808 lines
18 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2014 Freescale Semiconductor, Inc.
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/dts-v1/;
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#include "imx6sx.dtsi"
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/ {
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model = "Freescale i.MX6 SoloX Sabre Auto Board";
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compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_led>;
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user {
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label = "debug";
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gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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vcc_sd3: regulator-vcc-sd3 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_vcc_sd3>;
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regulator-name = "VCC_SD3";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_can_wake: regulator-can-wake {
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compatible = "regulator-fixed";
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regulator-name = "can-wake";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_can_en: regulator-can-en {
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compatible = "regulator-fixed";
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regulator-name = "can-en";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <®_can_wake>;
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};
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reg_can_stby: regulator-can-stby {
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compatible = "regulator-fixed";
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regulator-name = "can-stby";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <®_can_en>;
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};
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reg_vref_3v3: regulator-adc-verf {
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compatible = "regulator-fixed";
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regulator-name = "vref-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_audio: cs42888_supply {
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compatible = "regulator-fixed";
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regulator-name = "cs42888_supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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si4763_vio1: vio1_tnr {
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compatible = "regulator-fixed";
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regulator-name = "vio1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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si4763_vio2: vio2_tnr {
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compatible = "regulator-fixed";
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regulator-name = "vio2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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si4763_vd: f3v3_tnr {
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compatible = "regulator-fixed";
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regulator-name = "vd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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si4763_va: f5v_tnr {
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compatible = "regulator-fixed";
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regulator-name = "va";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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sound-cs42888 {
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compatible = "fsl,imx6-sabreauto-cs42888",
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"fsl,imx-audio-cs42888";
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model = "imx-cs42888";
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esai-controller = <&esai>;
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asrc-controller = <&asrc>;
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audio-codec = <&codec>;
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};
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sound-fm {
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compatible = "fsl,imx-audio-si476x",
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"fsl,imx-tuner-si476x";
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model = "imx-radio-si4763";
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ssi-controller = <&ssi2>;
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fm-controller = <&si476x_codec>;
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mux-int-port = <2>;
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mux-ext-port = <5>;
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};
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sound-spdif {
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compatible = "fsl,imx-audio-spdif";
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model = "imx-spdif";
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spdif-controller = <&spdif>;
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spdif-in;
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};
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};
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&adc1 {
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vref-supply = <®_vref_3v3>;
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status = "okay";
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};
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&adc2 {
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vref-supply = <®_vref_3v3>;
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status = "okay";
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};
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&anaclk2 {
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clock-frequency = <24576000>;
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};
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux_3>;
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status = "okay";
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};
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&clks {
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assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
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<&clks IMX6SX_PLL4_BYPASS>,
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<&clks IMX6SX_CLK_PLL4_POST_DIV>;
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assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
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<&clks IMX6SX_PLL4_BYPASS_SRC>;
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assigned-clock-rates = <0>, <0>, <24576000>;
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};
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&esai {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esai_2>;
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assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
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<&clks IMX6SX_CLK_ESAI_EXTAL>;
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assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&spdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spdif_3>;
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status = "okay";
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};
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&ssi2 {
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fsl,mode = "i2s-master";
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status = "okay";
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};
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&csi2 {
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status = "okay";
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port {
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csi2_ep: endpoint {
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remote-endpoint = <&vadc_ep>;
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};
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};
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};
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&dcic1 {
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dcic_id = <0>;
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dcic_mux = "dcic-lcdif1";
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status = "okay";
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};
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&dcic2 {
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dcic_id = <1>;
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dcic_mux = "dcic-lvds";
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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at803x,eee-disabled;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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at803x,eee-disabled;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can_stby>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can_stby>;
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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nand-on-flash-bbt;
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status = "okay";
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};
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&qspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi1_1>;
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status = "okay";
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ddrsmp=<2>;
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flash0: n25q256a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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};
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flash1: n25q256a@2 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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reg = <2>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart5 { /* for bluetooth */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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fsl,uart-has-rtscts;
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status = "okay";
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/* for DTE mode, add below change */
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/* fsl,dte-mode;*/
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/* pinctrl-0 = <&pinctrl_uart5dte>; */
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
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keep-power-in-suspend;
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wakeup-source;
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vmmc-supply = <&vcc_sd3>;
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status = "okay";
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};
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&usdhc4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4>;
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bus-width = <8>;
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cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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keep-power-in-suspend;
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wakeup-source;
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status = "okay";
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};
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&iomuxc {
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pinctrl_audmux_3: audmux-3 {
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fsl,pins = <
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MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0
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MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0
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MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0
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>;
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};
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pinctrl_egalax_int: egalax-intgrp {
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fsl,pins = <
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MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
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MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
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MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
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MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
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MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
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MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
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MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
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MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
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MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
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MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
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MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
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MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
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MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
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MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
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MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
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MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
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MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
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MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
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MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
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MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
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MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
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MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
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MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
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MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
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MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
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>;
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};
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pinctrl_esai_2: esaigrp-2 {
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fsl,pins = <
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MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
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MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
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MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
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MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
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MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
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MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
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MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
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MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
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MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
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MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
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>;
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};
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pinctrl_spdif_3: spdifgrp-3 {
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fsl,pins = <
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MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
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MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
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MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
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>;
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};
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
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MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
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MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
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MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
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MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
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MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
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MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
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MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
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MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
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MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
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MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
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MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
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MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
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MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
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MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
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MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
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MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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|
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
|
|
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_led: ledgrp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_qspi1_1: qspi1grp_1 {
|
|
fsl,pins = <
|
|
MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1
|
|
MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1
|
|
MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1
|
|
MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1
|
|
MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1
|
|
MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1
|
|
MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1
|
|
MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1
|
|
MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1
|
|
MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1
|
|
MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1
|
|
MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
|
|
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
|
|
MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5: uart5grp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
|
|
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
|
|
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
|
|
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5dte: uart5dtegrp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
|
|
MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
|
|
MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
|
|
MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
|
|
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
|
|
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
|
|
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
|
|
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
|
|
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
|
|
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
|
|
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
|
|
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
|
|
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
|
|
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
|
|
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
|
|
fsl,pins = <
|
|
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
|
|
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
|
|
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
|
|
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
|
|
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
|
|
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
|
|
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
|
|
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
|
|
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
|
|
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
|
|
fsl,pins = <
|
|
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
|
|
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
|
|
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
|
|
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
|
|
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
|
|
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
|
|
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
|
|
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
|
|
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
|
|
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc4: usdhc4grp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
|
|
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
|
|
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
|
|
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
|
|
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
|
|
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
|
|
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
|
|
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
|
|
>;
|
|
};
|
|
|
|
pinctrl_vcc_sd3: vccsd3grp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
|
|
>;
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
status = "okay";
|
|
|
|
codec: cs42888@48 {
|
|
compatible = "cirrus,cs42888";
|
|
reg = <0x48>;
|
|
clocks = <&anaclk2 0>;
|
|
clock-names = "mclk";
|
|
VA-supply = <®_audio>;
|
|
VD-supply = <®_audio>;
|
|
VLS-supply = <®_audio>;
|
|
VLC-supply = <®_audio>;
|
|
};
|
|
|
|
si4763: si4763@63 {
|
|
compatible = "si4761";
|
|
reg = <0x63>;
|
|
va-supply = <&si4763_va>;
|
|
vd-supply = <&si4763_vd>;
|
|
vio1-supply = <&si4763_vio1>;
|
|
vio2-supply = <&si4763_vio2>;
|
|
revision-a10; /* set to default A10 compatible command set */
|
|
|
|
si476x_codec: si476x-codec {
|
|
compatible = "si476x-codec";
|
|
};
|
|
};
|
|
|
|
touchscreen@4 {
|
|
compatible = "eeti,egalax_ts";
|
|
reg = <0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_egalax_int>;
|
|
interrupt-parent = <&gpio6>;
|
|
interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
|
|
wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
pfuze100: pmic@8 {
|
|
compatible = "fsl,pfuze100";
|
|
reg = <0x08>;
|
|
|
|
regulators {
|
|
sw1a_reg: sw1ab {
|
|
regulator-min-microvolt = <300000>;
|
|
regulator-max-microvolt = <1875000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <6250>;
|
|
};
|
|
|
|
sw1c_reg: sw1c {
|
|
regulator-min-microvolt = <300000>;
|
|
regulator-max-microvolt = <1875000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <6250>;
|
|
};
|
|
|
|
sw2_reg: sw2 {
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
sw3a_reg: sw3a {
|
|
regulator-min-microvolt = <400000>;
|
|
regulator-max-microvolt = <1975000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
sw3b_reg: sw3b {
|
|
regulator-min-microvolt = <400000>;
|
|
regulator-max-microvolt = <1975000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
sw4_reg: sw4 {
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
swbst_reg: swbst {
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5150000>;
|
|
};
|
|
|
|
snvs_reg: vsnvs {
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <3000000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vref_reg: vrefddr {
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen1_reg: vgen1 {
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1550000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen2_reg: vgen2 {
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1550000>;
|
|
};
|
|
|
|
vgen3_reg: vgen3 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen4_reg: vgen4 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen5_reg: vgen5 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen6_reg: vgen6 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
max7322: gpio@68 {
|
|
compatible = "maxim,max7322";
|
|
reg = <0x68>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&i2c3 {
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
status = "okay";
|
|
|
|
max7310_a: gpio@30 {
|
|
compatible = "maxim,max7310";
|
|
reg = <0x30>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
max7310_b: gpio@32 {
|
|
compatible = "maxim,max7310";
|
|
reg = <0x32>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
mma8451@1c {
|
|
compatible = "fsl,mma8451";
|
|
reg = <0x1c>;
|
|
position = <7>;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <24 8>;
|
|
interrupt-route = <1>;
|
|
};
|
|
|
|
mag3110@e {
|
|
compatible = "fsl,mag3110";
|
|
reg = <0xe>;
|
|
position = <2>;
|
|
interrupt-parent = <&gpio6>;
|
|
interrupts = <6 1>;
|
|
};
|
|
|
|
isl29023@44 {
|
|
compatible = "fsl,isl29023";
|
|
reg = <0x44>;
|
|
rext = <499>;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <23 2>;
|
|
};
|
|
};
|
|
|
|
&vadc {
|
|
vadc_in = <0>;
|
|
csi_id = <1>;
|
|
status = "okay";
|
|
port {
|
|
vadc_ep: endpoint {
|
|
remote-endpoint = <&csi2_ep>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
};
|