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37c045d25e
The 1.5 version of Engicam's i.Core MX6 CPU module features a different clock provider for the ethernet's PHY interface. Adjust the FEC ptp clock to reference CLK_ENET_REF clock source, and set SION bit of MX6QDL_PAD_GPIO_16__ENET_REF_CLK to adjust the input path of that pin. The newly introduced imx6ql-icore-1.5.dtsi allows to collect in a single place differences between version '1.0' and '1.5' of the module. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
35 lines
901 B
Plaintext
35 lines
901 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Jacopo Mondi <jacopo@jmondi.org>
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*/
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#include "imx6qdl-icore.dtsi"
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&iomuxc {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
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>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
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clocks = <&clks IMX6QDL_CLK_ENET>,
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<&clks IMX6QDL_CLK_ENET>,
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<&clks IMX6QDL_CLK_ENET_REF>;
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phy-mode = "rmii";
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status = "okay";
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};
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