mirror of
https://github.com/brain-hackers/linux-brain.git
synced 2024-06-09 23:36:23 +09:00
925d5e4268
Use the new bindings of the Marvell NAND controller driver. Also adapt the NAND controller node organization to distinguish which property is relevant for the controller, and which one is NAND chip specific. Expose the partitions as a subnode of the NAND chip. Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as the new driver activates the arbiter by default for all boards which is either needed or harmless. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
177 lines
2.9 KiB
Plaintext
177 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Device Tree file for Marvell Armada 388 evaluation board
|
|
* (DB-88F6820)
|
|
*
|
|
* Copyright (C) 2014 Marvell
|
|
*
|
|
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include "armada-388.dtsi"
|
|
|
|
/ {
|
|
model = "Marvell Armada 385 Development Board";
|
|
compatible = "marvell,a385-db", "marvell,armada388",
|
|
"marvell,armada385", "marvell,armada380";
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x10000000>; /* 256 MB */
|
|
};
|
|
|
|
soc {
|
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
|
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
|
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
|
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
|
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
|
|
|
internal-regs {
|
|
i2c@11000 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c@11100 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
serial@12000 {
|
|
status = "okay";
|
|
};
|
|
|
|
ethernet@30000 {
|
|
status = "okay";
|
|
phy = <&phy1>;
|
|
phy-mode = "rgmii-id";
|
|
buffer-manager = <&bm>;
|
|
bm,pool-long = <2>;
|
|
bm,pool-short = <3>;
|
|
};
|
|
|
|
usb@58000 {
|
|
status = "ok";
|
|
};
|
|
|
|
ethernet@70000 {
|
|
status = "okay";
|
|
phy = <&phy0>;
|
|
phy-mode = "rgmii-id";
|
|
buffer-manager = <&bm>;
|
|
bm,pool-long = <0>;
|
|
bm,pool-short = <1>;
|
|
};
|
|
|
|
mdio@72004 {
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
phy1: ethernet-phy@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
sata@a8000 {
|
|
status = "okay";
|
|
};
|
|
|
|
sata@e0000 {
|
|
status = "okay";
|
|
};
|
|
|
|
bm@c8000 {
|
|
status = "okay";
|
|
};
|
|
|
|
sdhci@d8000 {
|
|
broken-cd;
|
|
wp-inverted;
|
|
bus-width = <8>;
|
|
status = "okay";
|
|
no-1-8-v;
|
|
};
|
|
|
|
usb3@f0000 {
|
|
status = "okay";
|
|
};
|
|
|
|
usb3@f8000 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
bm-bppi {
|
|
status = "okay";
|
|
};
|
|
|
|
pcie {
|
|
status = "okay";
|
|
/*
|
|
* The two PCIe units are accessible through
|
|
* standard PCIe slots on the board.
|
|
*/
|
|
pcie@1,0 {
|
|
/* Port 0, Lane 0 */
|
|
status = "okay";
|
|
};
|
|
pcie@2,0 {
|
|
/* Port 1, Lane 0 */
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
spi-flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "w25q32", "jedec,spi-nor";
|
|
reg = <0>; /* Chip select 0 */
|
|
spi-max-frequency = <108000000>;
|
|
};
|
|
};
|
|
|
|
&nand_controller {
|
|
status = "okay";
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
label = "pxa3xx_nand-0";
|
|
nand-rb = <0>;
|
|
marvell,nand-keep-config;
|
|
nand-on-flash-bbt;
|
|
nand-ecc-strength = <4>;
|
|
nand-ecc-step-size = <512>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "U-Boot";
|
|
reg = <0 0x800000>;
|
|
};
|
|
partition@800000 {
|
|
label = "Linux";
|
|
reg = <0x800000 0x800000>;
|
|
};
|
|
partition@1000000 {
|
|
label = "Filesystem";
|
|
reg = <0x1000000 0x3f000000>;
|
|
};
|
|
};
|
|
};
|
|
};
|