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4c3cfe14c0
This reverts commit 6c5be4ac63.
This commit was accidentally promoted twice
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
114 lines
4.9 KiB
C
114 lines
4.9 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_OPTC_DCN20_H__
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#define __DC_OPTC_DCN20_H__
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#include "../dcn10/dcn10_optc.h"
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#define TG_COMMON_REG_LIST_DCN2_0(inst) \
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TG_COMMON_REG_LIST_DCN(inst),\
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SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
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SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
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SRI(OTG_GSL_WINDOW_X, OTG, inst),\
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SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
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SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
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SRI(OTG_DSC_START_POSITION, OTG, inst),\
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SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
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SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
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SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
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SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
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SR(DWB_SOURCE_SELECT),\
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SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
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#define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
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TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
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SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
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SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
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SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
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SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
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SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
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SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
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SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
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SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
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SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
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SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
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SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
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SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
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SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
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SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
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SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
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SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
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SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
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SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
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SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
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SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
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SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
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SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
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SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
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SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
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SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
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SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
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SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
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SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
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SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh)
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void dcn20_timing_generator_init(struct optc *optc);
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bool optc2_enable_crtc(struct timing_generator *optc);
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void optc2_set_gsl(struct timing_generator *optc,
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const struct gsl_params *params);
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void optc2_set_gsl_source_select(struct timing_generator *optc,
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int group_idx,
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uint32_t gsl_ready_signal);
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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void optc2_set_dsc_config(struct timing_generator *optc,
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enum optc_dsc_mode dsc_mode,
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uint32_t dsc_bytes_per_pixel,
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uint32_t dsc_slice_width);
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#endif
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void optc2_set_odm_bypass(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing);
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void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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struct dc_crtc_timing *timing);
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void optc2_get_optc_source(struct timing_generator *optc,
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uint32_t *num_of_src_opp,
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uint32_t *src_opp_id_0,
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uint32_t *src_opp_id_1);
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void optc2_triplebuffer_lock(struct timing_generator *optc);
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void optc2_triplebuffer_unlock(struct timing_generator *optc);
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void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
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void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
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void optc2_program_manual_trigger(struct timing_generator *optc);
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#endif /* __DC_OPTC_DCN20_H__ */
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