255 lines
6.1 KiB
Plaintext
255 lines
6.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2018 NXP
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/s32v234-clock.h>
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#include <dt-bindings/pinctrl/s32v234-pinctrl.h>
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/memreserve/ 0x80000000 0x00010000;
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/ {
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compatible = "fsl,s32v234";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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can0 = &can0;
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can1 = &can1;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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firc {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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fxosc {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x80000000>;
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next-level-cache = <&cluster0_l2_cache>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x80000000>;
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next-level-cache = <&cluster0_l2_cache>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x80000000>;
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next-level-cache = <&cluster1_l2_cache>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x80000000>;
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next-level-cache = <&cluster1_l2_cache>;
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};
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cluster0_l2_cache: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2_cache: l2-cache1 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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/* clock-frequency might be modified by u-boot, depending on the
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* chip version.
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*/
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clock-frequency = <10000000>;
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};
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gic: interrupt-controller@7d001000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x7d001000 0 0x1000>,
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<0 0x7d002000 0 0x2000>,
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<0 0x7d004000 0 0x2000>,
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<0 0x7d006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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aips0: aips-bus@40000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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reg = <0x0 0x40000000 0x0 0x7d000>;
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ranges;
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fec: ethernet@40032000 {
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compatible = "fsl,s32v234-fec";
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reg = <0x0 0x40032000 0x0 0x1000>;
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interrupt-names = "int0", "int1", "int2", "pps";
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks S32V234_CLK_SYS6>,
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<&clks S32V234_CLK_SYS3>,
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<&clks S32V234_CLK_ENET_TIME>,
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<&clks S32V234_CLK_ENET>,
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<&clks S32V234_CLK_ENET_TIME>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref",
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"enet_out";
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fsl,num-tx-queues = <3>;
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fsl,num-rx-queues = <3>;
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status = "disabled";
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};
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clks: mc_cgm0@4003c000 {
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compatible = "fsl,s32v234-mc_cgm0";
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reg = <0x0 0x4003C000 0x0 0x1000>;
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#clock-cells = <1>;
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};
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mc_cgm1: mc_cgm1@4003F000 {
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compatible = "fsl,s32v234-mc_cgm1";
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reg = <0x0 0x4003F000 0x0 0x1000>;
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};
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mc_cgm2: mc_cgm2@40042000 {
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compatible = "fsl,s32v234-mc_cgm2";
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reg = <0x0 0x40042000 0x0 0x1000>;
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};
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mc_cgm3: mc_cgm3@40045000 {
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compatible = "fsl,s32v234-mc_cgm3";
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reg = <0x0 0x40045000 0x0 0x1000>;
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};
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mc_me: mc_me@4004a000 {
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compatible = "fsl,s32v234-mc_me";
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reg = <0x0 0x4004A000 0x0 0x1000>;
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};
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uart0: serial@40053000 {
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compatible = "fsl,s32v234-linflexuart";
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reg = <0x0 0x40053000 0x0 0x1000>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clks S32V234_CLK_LIN>;
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clock-names = "lin";
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status = "disabled";
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};
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can0: flexcan@40055000 {
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compatible = "fsl,s32v234-flexcan";
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reg = <0x0 0x40055000 0x0 0x1000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks S32V234_CLK_CAN>,
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<&clks S32V234_CLK_CAN>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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usdhc0: usdhc@4005d000 {
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compatible = "fsl,s32v234-usdhc";
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reg = <0x0 0x4005D000 0x0 0x1000>;
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interrupts = <0 28 4>;
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clocks = <&clks S32V234_CLK_SDHC>,
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<&clks S32V234_CLK_SDHC>,
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<&clks S32V234_CLK_SDHC>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <8>;
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status = "disabled";
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};
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siul2: siul@4006c000 {
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compatible = "fsl,s32v234-siul2";
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reg = <0x0 0x4006C000 0x0 0x1794>;
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status = "disabled";
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};
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src: src@4007c000 {
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compatible = "fsl,s32v234-src";
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reg = <0x0 0x4007C000 0x0 0x1000>;
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#reset-cells = <1>;
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};
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};
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aips1: aips-bus@40080000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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reg = <0x0 0x40080000 0x0 0x70000>;
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ranges;
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uart1: serial@400bc000 {
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compatible = "fsl,s32v234-linflexuart";
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reg = <0x0 0x400bc000 0x0 0x1000>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clks S32V234_CLK_LIN>;
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clock-names = "lin";
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status = "disabled";
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};
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can1: flexcan@400be000 {
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compatible = "fsl,s32v234-flexcan";
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reg = <0x0 0x400be000 0x0 0x1000>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks S32V234_CLK_CAN>,
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<&clks S32V234_CLK_CAN>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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};
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};
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