100 lines
2.0 KiB
Plaintext
100 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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/ {
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panel {
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compatible = "sii,43wvf1g";
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backlight = <&lcdif_backlight>;
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status = "okay";
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port {
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lcd_panel_in: endpoint {
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remote-endpoint = <&lcd_display_out>;
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};
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};
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};
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display@disp1 {
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compatible = "fsl,imx-lcdif-mux-display";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif>;
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clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>,
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<&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
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clock-names = "bypass_div", "pixel";
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assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
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assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
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fsl,lcdif-mux-regs = <&lcdif_mux_regs>;
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fsl,interface-pix-fmt = "rgb666";
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power-domains = <&pd IMX_SC_R_LCD_0>;
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status = "okay";
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port@0 {
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reg = <0>;
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lcd_display_in: endpoint {
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remote-endpoint = <&dpu_disp1_lcdif>;
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};
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};
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port@1 {
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reg = <1>;
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lcd_display_out: endpoint {
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remote-endpoint = <&lcd_panel_in>;
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};
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};
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};
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lcdif_backlight: lcdif-backlight {
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compatible = "pwm-backlight";
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pwms = <&adma_pwm 0 100000 0>;
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brightness-levels = < 0 1 2 3 4 5 6 7 8 9
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10 11 12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27 28 29
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30 31 32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47 48 49
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50 51 52 53 54 55 56 57 58 59
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60 61 62 63 64 65 66 67 68 69
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70 71 72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87 88 89
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90 91 92 93 94 95 96 97 98 99
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100>;
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default-brightness-level = <80>;
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};
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};
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&dpu_disp1_lcdif {
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remote-endpoint = <&lcd_display_in>;
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};
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&iomuxc {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000
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>;
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};
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};
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&sai1 {
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status = "disabled";
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};
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&esai0 {
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status = "disabled";
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};
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&lpuart1 {
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status = "disabled";
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};
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&adma_pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdifpwm>;
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status = "okay";
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};
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