22 lines
556 B
Plaintext
22 lines
556 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Richard Zhu <hongxing.zhu@nxp.com>
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*/
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&hsio_subsys {
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phyx1_lpcg: clock-controller@5f090000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f090000 0x10000>;
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#clock-cells = <1>;
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clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
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<&hsio_per_clk>, <&hsio_per_clk>;
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bit-offset = <0 4 8 16>;
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clock-output-names = "hsio_phyx1_pclk",
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"hsio_phyx1_epcs_tx_clk",
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"hsio_phyx1_epcs_rx_clk",
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"hsio_phyx1_apb_clk";
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power-domains = <&pd IMX_SC_R_SERDES_1>;
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};
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};
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