78 lines
1.5 KiB
Plaintext
78 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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&dma_ipg_clk {
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clock-frequency = <160000000>;
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};
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&audio_ipg_clk {
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clock-frequency = <160000000>;
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};
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&lpuart0 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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};
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&lpuart1 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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};
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&lpuart2 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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};
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&lpuart3 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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};
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&i2c0 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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};
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&i2c1 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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};
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&i2c2 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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};
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&i2c3 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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};
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&audio_subsys {
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dsp: dsp@596e8000 {
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compatible = "fsl,imx8qxp-dsp";
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reg = <0x596e8000 0x88000>;
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clocks = <&dsp_lpcg 1>,
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<&dsp_ram_lpcg 0>,
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<&dsp_lpcg 2>;
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clock-names = "ipg", "ocram", "core";
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fsl,dsp-firmware = "imx/dsp/hifi4.bin";
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power-domains = <&pd IMX_SC_R_MU_13A>,
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<&pd IMX_SC_R_MU_13B>,
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<&pd IMX_SC_R_DSP>,
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<&pd IMX_SC_R_DSP_RAM>,
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<&pd IMX_SC_R_IRQSTR_DSP>;
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mbox-names = "txdb0", "txdb1",
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"rxdb0", "rxdb1";
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mboxes = <&lsio_mu13 2 0>,
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<&lsio_mu13 2 1>,
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<&lsio_mu13 3 0>,
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<&lsio_mu13 3 1>;
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status = "disabled";
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};
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};
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&dma_subsys {
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lcdif_mux_regs: mux-regs@5a170000 {
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compatible = "fsl,imx8qxp-lcdif-mux-regs", "syscon";
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reg = <0x5a170000 0x4>;
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};
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};
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