51 lines
1.3 KiB
Plaintext
51 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*/
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#include "imx8qxp-lpddr4-val.dts"
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&iomuxc {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c
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IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c
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IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c
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IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c
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IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c
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IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c
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IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c
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IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c
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IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c
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IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c
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IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c
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IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c
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IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c
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IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c
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IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c
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/* i.MX8QXP NAND use nand_re_dqs_pins */
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IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c
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IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c
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>;
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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status = "okay";
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nand-on-flash-bbt;
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};
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/* Disabled the usdhc1/usdhc2 since pin conflict */
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&usdhc1 {
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status = "disabled";
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};
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&usdhc2 {
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status = "disabled";
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};
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