353 lines
9.4 KiB
Plaintext
353 lines
9.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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/ {
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dsi_ipg_clk: clock-dsi-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <120000000>;
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clock-output-names = "dsi_ipg_clk";
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};
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mipi_pll_div2_clk: clock-mipi-div2-pll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <432000000>;
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clock-output-names = "mipi_pll_div2_clk";
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};
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mipi0_subsys: bus@56220000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x56220000 0x0 0x56220000 0x10000>;
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mipi0_lis_lpcg: clock-controller@56223000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223000 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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bit-offset = <0>;
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clock-output-names = "mipi0_lis_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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};
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mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5622301c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
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bit-offset = <0>;
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clock-output-names = "mipi0_i2c0_lpcg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
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};
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mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223018 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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bit-offset = <0>;
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clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
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};
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mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223014 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi0_i2c0_lpcg_ipg_s_clk 0>;
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bit-offset = <0>;
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clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
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};
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mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5622302c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
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bit-offset = <0>;
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clock-output-names = "mipi0_i2c1_lpcg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
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};
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mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223028 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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bit-offset = <0>;
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clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
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};
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mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223024 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi0_i2c1_lpcg_ipg_s_clk 0>;
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bit-offset = <0>;
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clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
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};
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irqsteer_mipi0: irqsteer@56220000 {
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compatible = "fsl,imx-irqsteer";
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reg = <0x56220000 0x1000>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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clocks = <&mipi0_lis_lpcg 0>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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};
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i2c0_mipi0: i2c@56226000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x56226000 0x1000>;
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interrupts = <8>;
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interrupt-parent = <&irqsteer_mipi0>;
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clocks = <&mipi0_i2c0_lpcg_clk 0>,
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<&mipi0_i2c0_lpcg_ipg_clk 0>;
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clock-names = "per", "ipg";
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assigned-clocks = <&mipi0_i2c0_lpcg_clk 0>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
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status = "disabled";
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};
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mipi0_csr: csr@56221000 {
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compatible = "syscon";
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reg = <0x56221000 0x240>;
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};
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mipi0_dphy: dphy@56228300 {
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compatible = "fsl,imx8qm-mipi-dphy";
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reg = <0x56228300 0x100>;
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clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>;
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clock-names = "phy_ref";
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#phy-cells = <0>;
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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status = "disabled";
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};
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mipi0_dsi_host: dsi_host@56228000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qm-nwl-dsi";
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reg = <0x56228000 0x300>;
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clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>,
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<&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>,
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<&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
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<&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>,
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<&mipi_pll_div2_clk>;
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clock-names = "pixel",
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"bypass",
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"phy_ref",
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"tx_esc",
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"rx_esc",
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"phy_parent";
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interrupts = <16>;
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interrupt-parent = <&irqsteer_mipi0>;
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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phys = <&mipi0_dphy>;
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phy-names = "dphy";
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csr = <&mipi0_csr>;
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use-disp-ss;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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mipi0_dsi_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dpu1_disp0_mipi0>;
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};
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};
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};
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};
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};
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mipi1_subsys: bus@57220000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x57220000 0x0 0x57220000 0x10000>;
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mipi1_lis_lpcg: clock-controller@57223000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223000 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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bit-offset = <0>;
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clock-output-names = "mipi1_lis_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1>;
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};
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mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5722301c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
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bit-offset = <0>;
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clock-output-names = "mipi1_i2c0_lpcg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
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};
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mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223018 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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bit-offset = <0>;
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clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
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};
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mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223014 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi1_i2c0_lpcg_ipg_s_clk 0>;
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bit-offset = <0>;
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clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
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};
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mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5722302c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
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bit-offset = <0>;
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clock-output-names = "mipi1_i2c1_lpcg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
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};
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mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223028 0x4>;
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#clock-cells = <1>;
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clocks = <&dsi_ipg_clk>;
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bit-offset = <0>;
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clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
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};
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mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57223024 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi1_i2c1_lpcg_ipg_s_clk 0>;
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bit-offset = <0>;
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clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
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};
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irqsteer_mipi1: irqsteer@57220000 {
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compatible = "fsl,imx-irqsteer";
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reg = <0x57220000 0x1000>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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clocks = <&mipi1_lis_lpcg 0>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_MIPI_1>;
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};
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i2c0_mipi1: i2c@57226000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x57226000 0x1000>;
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interrupts = <8>;
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interrupt-parent = <&irqsteer_mipi1>;
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clocks = <&mipi1_i2c0_lpcg_clk 0>,
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<&mipi1_i2c0_lpcg_ipg_clk 0>;
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clock-names = "per", "ipg";
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assigned-clocks = <&mipi1_i2c0_lpcg_clk 0>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
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status = "disabled";
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};
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mipi1_csr: csr@57221000 {
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compatible = "syscon";
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reg = <0x57221000 0x240>;
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};
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mipi1_dphy: dphy@57228300 {
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compatible = "fsl,imx8qm-mipi-dphy";
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reg = <0x57228300 0x100>;
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clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>;
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clock-names = "phy_ref";
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#phy-cells = <0>;
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power-domains = <&pd IMX_SC_R_MIPI_1>;
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status = "disabled";
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};
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mipi1_dsi_host: dsi_host@57228000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qm-nwl-dsi";
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reg = <0x57228000 0x300>;
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clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>,
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<&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>,
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<&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
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<&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>,
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<&mipi_pll_div2_clk>;
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clock-names = "pixel",
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"bypass",
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"phy_ref",
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"tx_esc",
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"rx_esc",
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"phy_parent";
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interrupts = <16>;
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interrupt-parent = <&irqsteer_mipi1>;
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power-domains = <&pd IMX_SC_R_MIPI_1>;
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phys = <&mipi1_dphy>;
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phy-names = "dphy";
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csr = <&mipi1_csr>;
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use-disp-ss;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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mipi1_dsi_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dpu2_disp0_mipi1>;
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};
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};
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};
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};
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};
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};
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