791 lines
13 KiB
Plaintext
791 lines
13 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include "imx8qm-mek.dts"
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#include "imx8qm-xen.dtsi"
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/ {
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model = "Freescale i.MX8QM MEK";
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compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
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chosen {
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#address-cells = <2>;
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#size-cells = <2>;
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stdout-path = &lpuart0;
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/* Could be updated by U-Boot */
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module@0 {
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bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait";
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compatible = "xen,linux-zimage", "xen,multiboot-module";
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reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>;
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};
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};
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domu {
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/*
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* There are 5 MUs, 0A is used by Dom0, 1A is used
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* by ATF, so for DomU, 2A/3A/4A could be used.
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* SC_R_MU_0A
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* SC_R_MU_1A
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* SC_R_MU_2A
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* SC_R_MU_3A
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* SC_R_MU_4A
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* The rsrcs and pads will be configured by uboot scu_rm cmd
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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doma {
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compatible = "xen,domu";
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/*
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* The name entry in VM configuration file
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* needs to be same as here.
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*/
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domain_name = "DomU";
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/*
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* The reg property will be updated by U-Boot to
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* reflect the partition id.
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*/
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reg = <0>;
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init_on_rsrcs = <
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IMX_SC_R_MU_2A
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>;
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rsrcs = <
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IMX_SC_R_MU_2A
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IMX_SC_R_GPU_0_PID0
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IMX_SC_R_GPU_0_PID1
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IMX_SC_R_GPU_0_PID2
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IMX_SC_R_GPU_0_PID3
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IMX_SC_R_LVDS_0
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IMX_SC_R_LVDS_0_I2C_0
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IMX_SC_R_LVDS_0_PWM_0
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IMX_SC_R_DC_0
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IMX_SC_R_DC_0_BLIT0
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IMX_SC_R_DC_0_BLIT1
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IMX_SC_R_DC_0_BLIT2
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IMX_SC_R_DC_0_BLIT_OUT
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IMX_SC_R_DC_0_WARP
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IMX_SC_R_DC_0_VIDEO0
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IMX_SC_R_DC_0_VIDEO1
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IMX_SC_R_DC_0_FRAC0
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IMX_SC_R_DC_0_PLL_0
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IMX_SC_R_DC_0_PLL_1
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IMX_SC_R_SDHC_0
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/*vpu*/
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IMX_SC_R_VPU_PID0
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IMX_SC_R_VPU_PID1
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IMX_SC_R_VPU_PID2
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IMX_SC_R_VPU_PID3
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IMX_SC_R_VPU_PID4
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IMX_SC_R_VPU_PID5
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IMX_SC_R_VPU_PID6
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IMX_SC_R_VPU_PID7
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IMX_SC_R_VPU
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IMX_SC_R_VPU_DEC_0
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IMX_SC_R_VPU_ENC_0
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IMX_SC_R_VPU_ENC_1
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IMX_SC_R_VPU_TS_0
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IMX_SC_R_VPU_MU_0
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IMX_SC_R_VPU_MU_1
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IMX_SC_R_VPU_MU_2
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IMX_SC_R_VPU_MU_3
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IMX_SC_R_MU_13A
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IMX_SC_R_MU_13B
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IMX_SC_R_DSP
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IMX_SC_R_DSP_RAM
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/* usbotg1 */
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IMX_SC_R_USB_0
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IMX_SC_R_USB_0_PHY
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/* usbotg3 */
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IMX_SC_R_USB_2
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IMX_SC_R_USB_2_PHY
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/* ASRC0 */
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IMX_SC_R_DMA_2_CH0
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IMX_SC_R_DMA_2_CH1
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IMX_SC_R_DMA_2_CH2
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IMX_SC_R_DMA_2_CH3
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IMX_SC_R_DMA_2_CH4
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IMX_SC_R_DMA_2_CH5
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IMX_SC_R_DMA_2_CH6
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IMX_SC_R_DMA_2_CH7
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IMX_SC_R_DMA_2_CH8
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IMX_SC_R_DMA_2_CH9
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IMX_SC_R_DMA_2_CH10
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IMX_SC_R_DMA_2_CH11
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IMX_SC_R_DMA_2_CH12
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IMX_SC_R_DMA_2_CH13
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IMX_SC_R_DMA_2_CH14
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IMX_SC_R_DMA_2_CH15
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IMX_SC_R_DMA_2_CH16
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IMX_SC_R_DMA_2_CH17
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IMX_SC_R_DMA_2_CH18
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IMX_SC_R_DMA_2_CH19
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IMX_SC_R_DMA_2_CH20
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IMX_SC_R_AUDIO_CLK_0
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IMX_SC_R_AUDIO_CLK_1
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IMX_SC_R_MCLK_OUT_0
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IMX_SC_R_MCLK_OUT_1
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IMX_SC_R_AUDIO_PLL_0
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IMX_SC_R_AUDIO_PLL_1
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IMX_SC_R_ASRC_0
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IMX_SC_R_ASRC_1
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IMX_SC_R_ESAI_0
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IMX_SC_R_ESAI_1
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IMX_SC_R_SAI_0
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IMX_SC_R_SAI_1
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IMX_SC_R_SAI_2
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IMX_SC_R_SAI_3
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IMX_SC_R_SAI_4
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IMX_SC_R_SAI_5
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IMX_SC_R_SAI_6
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IMX_SC_R_SAI_7
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IMX_SC_R_SPDIF_0
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IMX_SC_R_SPDIF_1
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IMX_SC_R_MQS_0
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IMX_SC_R_DMA_3_CH0
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IMX_SC_R_DMA_3_CH1
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IMX_SC_R_DMA_3_CH2
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IMX_SC_R_DMA_3_CH3
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IMX_SC_R_DMA_3_CH4
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IMX_SC_R_DMA_3_CH5
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IMX_SC_R_DMA_3_CH6
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IMX_SC_R_DMA_3_CH7
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IMX_SC_R_DMA_3_CH8
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IMX_SC_R_DMA_3_CH9
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IMX_SC_R_DMA_3_CH10
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IMX_SC_R_SATA_0
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IMX_SC_R_PCIE_A
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IMX_SC_R_PCIE_B
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IMX_SC_R_SERDES_0
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IMX_SC_R_SERDES_1
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IMX_SC_R_HSIO_GPIO
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IMX_SC_R_DMA_0_CH14
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IMX_SC_R_DMA_0_CH15
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IMX_SC_R_UART_1
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IMX_SC_R_MIPI_0
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IMX_SC_R_MIPI_0_I2C_0
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IMX_SC_R_MIPI_0_I2C_1
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IMX_SC_R_MIPI_1
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IMX_SC_R_MIPI_1_I2C_0
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IMX_SC_R_MIPI_1_I2C_1
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IMX_SC_R_HDMI_PLL_0
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IMX_SC_R_HDMI_PLL_1
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IMX_SC_R_HDMI
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IMX_SC_R_HDMI_I2C_0
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IMX_SC_R_HDMI_I2S
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IMX_SC_R_CSI_0
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IMX_SC_R_CSI_0_I2C_0
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IMX_SC_R_CSI_1
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IMX_SC_R_CSI_1_I2C_0
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IMX_SC_R_ISI_CH0
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IMX_SC_R_ISI_CH1
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IMX_SC_R_ISI_CH2
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IMX_SC_R_ISI_CH3
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IMX_SC_R_ISI_CH4
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IMX_SC_R_ISI_CH5
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IMX_SC_R_ISI_CH6
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IMX_SC_R_ISI_CH7
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IMX_SC_R_MJPEG_DEC_MP
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IMX_SC_R_MJPEG_DEC_S0
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IMX_SC_R_MJPEG_DEC_S1
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IMX_SC_R_MJPEG_DEC_S2
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IMX_SC_R_MJPEG_DEC_S3
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IMX_SC_R_MJPEG_ENC_MP
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IMX_SC_R_MJPEG_ENC_S0
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IMX_SC_R_MJPEG_ENC_S1
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IMX_SC_R_MJPEG_ENC_S2
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IMX_SC_R_MJPEG_ENC_S3
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>;
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pads = <
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/* i2c1_lvds1 */
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IMX8QM_LVDS0_I2C1_SCL
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IMX8QM_LVDS0_I2C1_SDA
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/* emmc */
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IMX8QM_EMMC0_CLK
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IMX8QM_EMMC0_CMD
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IMX8QM_EMMC0_DATA0
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IMX8QM_EMMC0_DATA1
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IMX8QM_EMMC0_DATA2
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IMX8QM_EMMC0_DATA3
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IMX8QM_EMMC0_DATA4
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IMX8QM_EMMC0_DATA5
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IMX8QM_EMMC0_DATA6
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IMX8QM_EMMC0_DATA7
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IMX8QM_EMMC0_STROBE
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IMX8QM_EMMC0_RESET_B
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/* lvds pwm */
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IMX8QM_LVDS0_GPIO00
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/* usbotg1/3 */
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IMX8QM_USB_SS3_TC0
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IMX8QM_QSPI1A_SS0_B
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IMX8QM_USB_SS3_TC3
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IMX8QM_QSPI1A_DATA0
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/* ESAI0 */
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IMX8QM_ESAI0_FSR
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IMX8QM_ESAI0_FST
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IMX8QM_ESAI0_SCKR
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IMX8QM_ESAI0_SCKT
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IMX8QM_ESAI0_TX0
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IMX8QM_ESAI0_TX1
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IMX8QM_ESAI0_TX2_RX3
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IMX8QM_ESAI0_TX3_RX2
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IMX8QM_ESAI0_TX4_RX1
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IMX8QM_ESAI0_TX5_RX0
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/* SAI1 */
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IMX8QM_SAI1_RXD
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IMX8QM_SAI1_RXC
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IMX8QM_SAI1_RXFS
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IMX8QM_SAI1_TXD
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IMX8QM_SAI1_TXC
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IMX8QM_PCIE_CTRL0_CLKREQ_B
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IMX8QM_PCIE_CTRL0_WAKE_B
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IMX8QM_PCIE_CTRL0_PERST_B
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IMX8QM_LVDS1_I2C0_SDA
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IMX8QM_USDHC2_RESET_B
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IMX8QM_QSPI1A_DQS
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IMX8QM_UART1_RX
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IMX8QM_UART1_TX
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IMX8QM_UART1_CTS_B
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IMX8QM_UART1_RTS_B
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IMX8QM_MIPI_CSI0_I2C0_SCL
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IMX8QM_MIPI_CSI0_I2C0_SDA
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IMX8QM_MIPI_CSI1_I2C0_SCL
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IMX8QM_MIPI_CSI1_I2C0_SDA
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IMX8QM_MIPI_CSI1_GPIO0_00
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IMX8QM_MIPI_CSI0_GPIO0_00
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IMX8QM_MIPI_CSI0_GPIO0_01
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IMX8QM_MIPI_CSI0_MCLK_OUT
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IMX8QM_USDHC2_WP
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IMX8QM_MIPI_DSI0_I2C0_SCL
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IMX8QM_MIPI_DSI0_I2C0_SDA
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IMX8QM_MIPI_DSI0_GPIO0_01
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IMX8QM_MIPI_DSI1_I2C0_SCL
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IMX8QM_MIPI_DSI1_I2C0_SDA
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IMX8QM_MIPI_DSI1_GPIO0_01
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IMX8QM_SCU_GPIO0_07
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IMX8QM_SPI0_CS1
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IMX8QM_SPI2_CS1
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IMX8QM_SAI1_RXFS
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IMX8QM_SAI1_RXC
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>;
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gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>,
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<&lsio_gpio1 19 GPIO_ACTIVE_LOW>,
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<&lsio_gpio1 27 GPIO_ACTIVE_LOW>,
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<&lsio_gpio1 28 GPIO_ACTIVE_LOW>,
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<&lsio_gpio1 30 GPIO_ACTIVE_LOW>,
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<&lsio_gpio4 1 GPIO_ACTIVE_LOW>,
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<&lsio_gpio4 3 GPIO_ACTIVE_LOW>,
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<&lsio_gpio4 6 GPIO_ACTIVE_LOW>,
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<&lsio_gpio4 9 GPIO_ACTIVE_LOW>,
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<&lsio_gpio4 11 GPIO_ACTIVE_HIGH>,
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<&lsio_gpio4 19 GPIO_ACTIVE_HIGH>,
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<&lsio_gpio4 22 GPIO_ACTIVE_LOW>,
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<&lsio_gpio4 25 GPIO_ACTIVE_HIGH>,
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<&lsio_gpio4 26 GPIO_ACTIVE_HIGH>,
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<&lsio_gpio4 27 GPIO_ACTIVE_LOW>,
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<&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
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};
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};
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/* Interrupt 33 is not used, use it virtual PL031 */
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rtc0: rtc@23000000 {
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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xen,passthrough;
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};
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gpio4_dummy: gpio4_dummy@0{
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/* Passthrough gpio4 interrupt to DomU */
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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xen,passthrough;
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};
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gpio1_dummy: gpio1_dummy@0{
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/* Passthrough gpio1 interrupt to DomU */
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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xen,passthrough;
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};
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reserved-device-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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decoder_boot@0x84000000 {
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no-map;
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reg = <0 0x84000000 0 0x2000000>;
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xen,passthrough;
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};
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encoder_boot@0x86000000 {
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no-map;
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reg = <0 0x86000000 0 0x400000>;
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xen,passthrough;
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};
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m4@0x88000000 {
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no-map;
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reg = <0 0x88000000 0 0x8000000>;
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xen,passthrough;
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};
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rpmsg@0x90000000 {
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no-map;
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reg = <0 0x90200000 0 0x200000>;
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xen,passthrough;
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};
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decoder_rpc@0x92000000 {
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no-map;
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reg = <0 0x92000000 0 0x200000>;
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xen,passthrough;
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};
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encoder_rpc@0x92200000 {
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no-map;
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reg = <0 0x92200000 0 0x200000>;
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xen,passthrough;
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};
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dsp@0x92400000 {
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no-map;
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reg = <0 0x92400000 0 0x2000000>;
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xen,passthrough;
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};
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encoder_reserved@0x94400000 {
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no-map;
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reg = <0 0x94400000 0 0x800000>;
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xen,passthrough;
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};
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ts_boot@0x95000000 {
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no-map;
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reg = <0 0x95000000 0 0x400000>;
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xen,passthrough;
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};
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};
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};
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&{/reserved-memory} {
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x3c000000>;
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alloc-ranges = <0 0xa8000000 0 0x58000000>;
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linux,cma-default;
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};
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};
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&smmu {
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mmu-masters = <&dpu1 0x13>, <&gpu_3d0 0x15>, <&usdhc1 0x12>, <&edma0 0x14>,
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<&vpu_decoder 0x7>, <&usbotg1 0x11>, <&usbotg3 0x4>,
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<&pciea 0x8>, <&edma214 0x10>, <&isi_0 0x5>;
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};
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&edma0 {
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#stream-id-cells = <1>;
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iommus = <&smmu>;
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xen,passthrough;
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};
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&gpu_3d0{
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#stream-id-cells = <1>;
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iommus = <&smmu>;
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xen,passthrough;
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};
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&gpu_3d1{
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status = "okay";
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};
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&imx8_gpu_ss {
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cores = <&gpu_3d1>;
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reg = <0xa8000000 0x58000000>, <0x0 0x10000000>;
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status = "okay";
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};
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&lsio_mu1 {
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/* not map for dom0, dom0 will mmio trap to xen */
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xen,no-map;
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};
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/ {
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&dpu2_disp0>, <&dpu2_disp1>;
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};
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};
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&dc0_irqsteer {
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reg = <0x56000000 0x20000>;
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xen,passthrough;
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};
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&dc0_pc {
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xen,passthrough;
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};
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&dc0_prg1 {
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xen,passthrough;
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};
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&dc0_prg2 {
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xen,passthrough;
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};
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&dc0_prg3 {
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xen,passthrough;
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};
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&dc0_prg4 {
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xen,passthrough;
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};
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&dc0_prg5 {
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xen,passthrough;
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};
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&dc0_prg6 {
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xen,passthrough;
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};
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&dc0_prg7 {
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xen,passthrough;
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};
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&dc0_prg8 {
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|
xen,passthrough;
|
|
};
|
|
|
|
&dc0_prg9 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&dc0_dpr1_channel1 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&dc0_dpr1_channel2 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&dc0_dpr1_channel3 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&dc0_dpr2_channel1 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&dc0_dpr2_channel2 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&dc0_dpr2_channel3 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&dpu1 {
|
|
xen,passthrough;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu>;
|
|
};
|
|
|
|
&irqsteer_lvds0 {
|
|
reg = <0x56240000 0x10000>;
|
|
xen,passthrough;
|
|
};
|
|
|
|
&lvds0_region {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&i2c1_lvds0 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&ldb1_phy {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&ldb1 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&usdhc1 {
|
|
xen,passthrough;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu>;
|
|
};
|
|
|
|
&sdhc0_lpcg {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&lsio_mu2 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&lsio_gpio1 {
|
|
/*
|
|
* Use GPT1 interrupt for hack
|
|
* This could be removed when interrupt sharing be supported.
|
|
*/
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
xen,domu-irq;
|
|
xen,shared;
|
|
};
|
|
|
|
/*
|
|
&gpt0 {
|
|
/delete-property/ interrupts;
|
|
status = "disabled";
|
|
};
|
|
*/
|
|
|
|
&lsio_gpio4 {
|
|
/*
|
|
* Use GPT0 interrupt for hack
|
|
* This could be removed when interrupt sharing be supported.
|
|
*/
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
xen,domu-irq;
|
|
xen,shared;
|
|
};
|
|
|
|
&gpio0_mipi_csi0 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&gpio0_mipi_csi1 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
/* vpu_subsys */
|
|
&vpu_lpcg {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&vpu_decoder {
|
|
xen,passthrough;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu>;
|
|
fsl,sc_rsrc_id = <IMX_SC_R_VPU_DEC_0>,
|
|
<IMX_SC_R_VPU_TS_0>,
|
|
<IMX_SC_R_VPU_PID0>,
|
|
<IMX_SC_R_VPU_PID1>,
|
|
<IMX_SC_R_VPU_PID2>,
|
|
<IMX_SC_R_VPU_PID3>,
|
|
<IMX_SC_R_VPU_PID4>,
|
|
<IMX_SC_R_VPU_PID5>,
|
|
<IMX_SC_R_VPU_PID6>,
|
|
<IMX_SC_R_VPU_PID7>;
|
|
};
|
|
|
|
&vpu_encoder {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&vpu_ts {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&dsp {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&lsio_mu13 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&mu_m0 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&mu1_m0 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&mu2_m0 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&mu3_m0 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&vpu_enc_core0 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&vpu_enc_core1 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&usbotg1 {
|
|
xen,passthrough;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu>;
|
|
};
|
|
|
|
&usbmisc1 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&usbphy1 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&usb2_lpcg {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&usbotg3 {
|
|
xen,passthrough;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu>;
|
|
};
|
|
|
|
&usb3phynop1 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&usb3_lpcg {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&ptn5110 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&{/cbtl04gp} {
|
|
status = "disabled";
|
|
};
|
|
|
|
&audio_subsys {
|
|
reg = <0 0x59000000 0 0x1000000>;
|
|
xen,passthrough;
|
|
};
|
|
|
|
/* Passthrough baseboard audio to DomU */
|
|
&cs42888 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
®_audio {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&{/sound-cs42888} {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&esai0 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&wm8960 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&hsio_subsys {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&pciea {
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu>;
|
|
xen,passthrough;
|
|
fsl,sc_rsrc_id = <IMX_SC_R_PCIE_A>;
|
|
};
|
|
|
|
&pcieb {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&epdev_on {
|
|
status = "disabled";
|
|
};
|
|
|
|
&lpuart1 {
|
|
xen,passthrough;
|
|
};
|
|
|
|
&modem_reset {
|
|
status = "disabled";
|
|
};
|
|
|
|
&edma214 {
|
|
xen,passthrough;
|
|
#stream-id-cells = <1>;
|
|
};
|
|
|
|
&hdmi_subsys {
|
|
xen,passthrough;
|
|
reg = <0 0x56260000 0 0x10000>;
|
|
};
|
|
|
|
&img_subsys {
|
|
xen,passthrough;
|
|
reg = <0 0x58000000 0 0x1000000>;
|
|
};
|
|
|
|
&mipi0_subsys {
|
|
xen,passthrough;
|
|
reg = <0 0x56220000 0 0x10000>;
|
|
};
|
|
|
|
&mipi1_subsys {
|
|
xen,passthrough;
|
|
reg = <0 0x57220000 0 0x10000>;
|
|
};
|
|
|
|
&isi_0 {
|
|
xen,passthrough;
|
|
#stream-id-cells = <1>;
|
|
iommus = <&smmu>;
|
|
fsl,sc_rsrc_id = <IMX_SC_R_ISI_CH0>,
|
|
<IMX_SC_R_ISI_CH1>,
|
|
<IMX_SC_R_ISI_CH2>,
|
|
<IMX_SC_R_ISI_CH3>,
|
|
<IMX_SC_R_ISI_CH4>,
|
|
<IMX_SC_R_ISI_CH5>,
|
|
<IMX_SC_R_ISI_CH6>,
|
|
<IMX_SC_R_ISI_CH7>,
|
|
<IMX_SC_R_ISI_CH0>,
|
|
<IMX_SC_R_MJPEG_DEC_S0>,
|
|
<IMX_SC_R_MJPEG_DEC_S1>,
|
|
<IMX_SC_R_MJPEG_DEC_S2>,
|
|
<IMX_SC_R_MJPEG_DEC_S3>,
|
|
<IMX_SC_R_MJPEG_ENC_S0>,
|
|
<IMX_SC_R_MJPEG_ENC_S1>,
|
|
<IMX_SC_R_MJPEG_ENC_S2>,
|
|
<IMX_SC_R_MJPEG_ENC_S3>;
|
|
};
|
|
|
|
&sc_pwrkey {
|
|
status = "disabled";
|
|
};
|
|
|
|
&pwm_lvds0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&uart0_lpcg {
|
|
status = "disabled";
|
|
};
|