73 lines
1.7 KiB
Plaintext
73 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2020 NXP
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*/
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#include "imx8mq-evk.dts"
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/ {
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modem_reset: modem-reset {
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reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
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};
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usdhc2_pwrseq: usdhc2_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
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};
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};
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&pinctrl_usdhc2 {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49
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MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46
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>;
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};
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&pinctrl_usdhc2_100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
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MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49
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>;
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};
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&pinctrl_usdhc2_200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
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MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49
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>;
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};
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&pcie0{
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status = "disabled";
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};
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&pcie1{
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status = "disabled";
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};
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&usdhc2 {
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pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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/delete-property/ cd-gpios;
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pm-ignore-notify;
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keep-power-in-suspend;
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non-removable;
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cap-power-off-card;
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mmc-pwrseq = <&usdhc2_pwrseq>;
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};
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