104 lines
1.8 KiB
Plaintext
104 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP.
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*/
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#include "imx8mq-evk.dts"
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/delete-node/&hdmi;
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&irqsteer {
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status = "okay";
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};
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&lcdif {
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status = "disabled";
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};
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&dcss {
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status = "okay";
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clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
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<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
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<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
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<&clk IMX8MQ_CLK_DC_PIXEL>,
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<&clk IMX8MQ_CLK_DISP_DTRC>;
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clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
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assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
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<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
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<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
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<&clk IMX8MQ_CLK_DISP_AXI>,
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<&clk IMX8MQ_CLK_DISP_RTRM>;
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assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
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<&clk IMX8MQ_VIDEO_PLL1>,
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<&clk IMX8MQ_CLK_27M>,
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<&clk IMX8MQ_SYS1_PLL_800M>,
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<&clk IMX8MQ_SYS1_PLL_800M>;
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assigned-clock-rates = <600000000>, <0>, <0>,
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<800000000>,
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<400000000>;
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port@0 {
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dcss_out: endpoint {
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remote-endpoint = <&mipi_dsi_in>;
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};
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};
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};
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&mipi_dsi {
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status = "okay";
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fsl,clock-drop-level = <2>;
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panel@0 {
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compatible = "raydium,rm67191";
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reg = <0>;
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pinctrl-0 = <&pinctrl_mipi_dsi_en>;
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pinctrl-names = "default";
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reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
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dsi-lanes = <4>;
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video-mode = <2>;
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width-mm = <68>;
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height-mm = <121>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&mipi_dsi_out>;
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mipi_dsi_in: endpoint {
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remote-endpoint = <&dcss_out>;
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};
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};
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port@1 {
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reg = <1>;
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mipi_dsi_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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&dphy {
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status = "okay";
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};
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&iomuxc {
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pinctrl_mipi_dsi_en: mipi_dsi_en {
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fsl,pins = <
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MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
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>;
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};
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};
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&synaptics_dsx_ts {
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status = "okay";
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};
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