99 lines
1.8 KiB
Plaintext
99 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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#include "imx8mp-evk.dts"
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/ {
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interrupt-parent = <&gic>;
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resmem: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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};
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};
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&cpu_pd_wait {
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/delete-property/ compatible;
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};
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&clk {
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init-on-array = <IMX8MP_CLK_USDHC3_ROOT
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IMX8MP_CLK_NAND_USDHC_BUS
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IMX8MP_CLK_HSIO_ROOT
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IMX8MP_CLK_UART4_ROOT
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IMX8MP_CLK_OCOTP_ROOT>;
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};
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&{/busfreq} {
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status = "disabled";
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};
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&{/reserved-memory} {
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jh_reserved: jh@fdc00000 {
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no-map;
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reg = <0 0xfdc00000 0x0 0x400000>;
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};
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loader_reserved: loader@fdb00000 {
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no-map;
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reg = <0 0xfdb00000 0x0 0x00100000>;
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};
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ivshmem_reserved: ivshmem@fda00000 {
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no-map;
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reg = <0 0xfda00000 0x0 0x00100000>;
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};
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ivshmem2_reserved: ivshmem2@fd900000 {
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no-map;
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reg = <0 0xfd900000 0x0 0x00100000>;
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};
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pci_reserved: pci@fd700000 {
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no-map;
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reg = <0 0xfd700000 0x0 0x00200000>;
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};
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inmate_reserved: inmate@c0000000 {
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no-map;
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reg = <0 0xc0000000 0x0 0x3d700000>;
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};
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};
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&iomuxc {
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
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MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
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>;
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};
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};
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&usdhc3 {
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status = "disabled";
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};
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&uart4 {
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/delete-property/ dmas;
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/delete-property/ dma-names;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "disabled";
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};
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&uart2 {
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/* uart4 is used by the 2nd OS, so configure pin and clk */
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pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>;
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assigned-clocks = <&clk IMX8MP_CLK_UART4>;
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assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
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};
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&usdhc2 {
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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};
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