85 lines
1.6 KiB
Plaintext
85 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 NXP.
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*/
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#include "imx8mn-evk.dts"
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/ {
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ext_osc_22m: ext-osc-22m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <22579200>;
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clock-output-names = "sclk0";
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};
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ext_osc_24m: ext-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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clock-output-names = "sclk1";
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};
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reg_3v3_vext: regulator-3v3-vext {
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compatible = "regulator-fixed";
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regulator-name = "3V3_VEXT";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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sound-micfil {
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status = "disabled";
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};
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sound-pcm512x {
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compatible = "fsl,imx-audio-pcm512x";
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model = "pcm512x-audio";
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audio-cpu = <&sai5>;
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audio-codec = <&pcm512x>;
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format = "i2s";
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audio-widgets =
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"Line", "Left Line Out Jack",
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"Line", "Right Line Out Jack";
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audio-routing =
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"Left Line Out Jack", "OUTL",
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"Right Line Out Jack", "OUTR";
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bitclock-master = <&pcm512x>;
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frame-master = <&pcm512x>;
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dac,24db_digital_gain;
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dac,led_status;
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};
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};
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&i2c3 {
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pcm512x: pcm512x@4d {
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compatible = "ti,pcm5122";
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reg = <0x4d>;
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AVDD-supply = <®_3v3_vext>;
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DVDD-supply = <®_3v3_vext>;
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CPVDD-supply = <®_3v3_vext>;
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clocks = <&ext_osc_22m>, <&ext_osc_24m>;
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clock-names = "sclk0", "sclk1";
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};
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};
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&iomuxc {
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imx8mn-evk {
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pinctrl_sai5: sai5grp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
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MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
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MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
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MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
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>;
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};
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};
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};
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&micfil {
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status = "disabled";
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};
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&sai5 {
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status = "okay";
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};
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