96 lines
1.8 KiB
Plaintext
96 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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#include "imx8mn-ddr4-evk.dts"
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/*
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TODO: need uncomment when linux ready
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&cpu_pd_wait {
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/delete-property/ compatible;
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};
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*/
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&{/} {
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x28000000>;
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alloc-ranges = <0 0x40000000 0 0x93c00000>;
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linux,cma-default;
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};
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ivshmem_reserved: ivshmem@0xbbb00000 {
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no-map;
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reg = <0 0xbbb00000 0x0 0x00100000>;
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};
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ivshmem2_reserved: ivshmem2@0xbba00000 {
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no-map;
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reg = <0 0xbba00000 0x0 0x00100000>;
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};
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pci_reserved: pci@0xbb800000 {
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no-map;
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reg = <0 0xbb800000 0x0 0x00200000>;
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};
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loader_reserved: loader@0xbb700000 {
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no-map;
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reg = <0 0xbb700000 0x0 0x00100000>;
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};
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jh_reserved: jh@0xb7c00000 {
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no-map;
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reg = <0 0xb7c00000 0x0 0x00400000>;
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};
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/* 512MB */
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inmate_reserved: inmate@0x93c00000 {
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no-map;
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reg = <0 0x93c00000 0x0 0x24000000>;
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};
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};
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};
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&iomuxc {
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/*
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* Used for the 2nd Linux.
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* TODO: M4 may use these pins.
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*/
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
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MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
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>;
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};
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};
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&clk {
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init-on-array = <IMX8MN_CLK_NAND_USDHC_BUS
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IMX8MN_CLK_USDHC3_ROOT
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IMX8MN_CLK_UART4_ROOT>;
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};
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&uart2 {
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pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>;
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assigned-clocks = <&clk IMX8MN_CLK_UART4>;
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assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
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};
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&usdhc3 {
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status = "disabled";
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};
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&usdhc2 {
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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};
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