113 lines
2.9 KiB
Plaintext
Executable File
113 lines
2.9 KiB
Plaintext
Executable File
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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vpu_subsys: bus@2c000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
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vpu_lpcg: clock-controller@2d000000 {
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compatible = "fsl,imx8qxp-lpcg-vpu";
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reg = <0x2c000000 0x2000000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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vpu_decoder: vpu_decoder@2c000000 {
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compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
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reg = <0x2c000000 0x1000000>;
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reg-names = "vpu_regs";
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power-domains = <&pd IMX_SC_R_VPU_DEC_0>,
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<&pd IMX_SC_R_VPU>;
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power-domain-names = "vpudec", "vpu";
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mbox-names = "tx0", "tx1", "rx";
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mboxes = <&mu_m0 0 0
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&mu_m0 0 1
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&mu_m0 1 0>;
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status = "disabled";
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};
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vpu_encoder: vpu_encoder@2d000000 {
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compatible = "nxp,imx8qxp-b0-vpuenc";
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reg = <0x2d000000 0x1000000>, /*VPU Encoder*/
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<0x2c000000 0x2000000>; /*VPU*/
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reg-names = "vpu_regs";
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power-domains = <&pd IMX_SC_R_VPU_ENC_0>,
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<&pd IMX_SC_R_VPU>;
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power-domain-names = "vpuenc1", "vpu";
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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vpu_ts: vpu_ts@2c000000 {
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compatible = "nxp,imx8qm-b0-vpu-ts";
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reg = <0x2c000000 0x1000000>;
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reg-names = "vpu_ts";
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power-domains = <&pd IMX_SC_R_VPU_TS_0>,
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<&pd IMX_SC_R_VPU>;
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power-domain-names = "vputs", "vpu";
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mbox-names = "ts_tx0", "ts_tx1", "ts_tx2", "ts_tx3",
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"ts_rx0", "ts_rx1", "ts_rx2", "ts_rx3";
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mboxes = <&mu3_m0 0 0
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&mu3_m0 0 1
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&mu3_m0 0 2
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&mu3_m0 0 3
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&mu3_m0 1 0
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&mu3_m0 1 1
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&mu3_m0 1 2
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&mu3_m0 1 3>;
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status = "disabled";
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};
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mu_m0: mailbox@2d000000 {
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compatible = "fsl,imx8-mu0-vpu-m0", "fsl,imx6sx-mu";
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reg = <0x2d000000 0x20000>;
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interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_0>;
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power-domain-names = "vpumu0";
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fsl,vpu_ap_mu_id = <16>;
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status = "okay";
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};
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mu1_m0: mailbox@2d020000 {
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compatible = "fsl,imx8-mu1-vpu-m0", "fsl,imx6sx-mu";
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reg = <0x2d020000 0x20000>;
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interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
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fsl,vpu_ap_mu_id = <17>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_1>;
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power-domain-names = "vpumu1";
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status = "okay";
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};
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mu2_m0: mailbox@2d040000 {
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compatible = "fsl,imx8-mu2-vpu-m0", "fsl,imx6sx-mu";
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reg = <0x2d040000 0x20000>;
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interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
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fsl,vpu_ap_mu_id = <18>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_2>;
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power-domain-names = "vpumu2";
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status = "disabled";
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};
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mu3_m0: mailbox@2d060000 {
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compatible = "fsl,imx8-mu3-vpu-m0", "fsl,imx6sx-mu";
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reg = <0x2d060000 0x20000>;
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interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
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fsl,vpu_ap_mu_id = <19>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_3>;
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power-domain-names = "vpumu3";
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status = "disabled";
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};
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};
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