88 lines
1.8 KiB
Plaintext
88 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Freescale LS2080a QDS Board.
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*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* Abhimanyu Saini <abhimanyu.saini@nxp.com>
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* Bhupesh Sharma <bhupesh.sharma@freescale.com>
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*
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*/
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/dts-v1/;
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#include "fsl-ls2080a.dtsi"
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#include "fsl-ls208xa-qds.dtsi"
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/ {
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model = "Freescale Layerscape 2080a QDS Board";
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compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&ifc {
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boardctrl: board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
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reg = <3 0 0x300>; /* TODO check address */
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ranges = <0 3 0 0x300>;
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mdio_mux_emi1 {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&emdio1>;
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reg = <0x54 1>; /* BRDCFG4 */
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mux-mask = <0xe0>; /* EMI1_MDIO */
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#address-cells=<1>;
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#size-cells = <0>;
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/* Child MDIO buses, one for each riser card:
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* reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
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* VSC8234 PHYs on the riser cards.
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*/
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mdio_mux3: mdio@60 {
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reg = <0x60>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio0_phy12: mdio_phy0@1c {
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reg = <0x1c>;
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phy-connection-type = "sgmii";
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};
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mdio0_phy13: mdio_phy1@1d {
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reg = <0x1d>;
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phy-connection-type = "sgmii";
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};
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mdio0_phy14: mdio_phy2@1e {
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reg = <0x1e>;
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phy-connection-type = "sgmii";
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};
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mdio0_phy15: mdio_phy3@1f {
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reg = <0x1f>;
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phy-connection-type = "sgmii";
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};
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};
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};
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};
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};
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/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
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&dpmac9 {
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phy-handle = <&mdio0_phy12>;
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};
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&dpmac10 {
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phy-handle = <&mdio0_phy13>;
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};
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&dpmac11 {
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phy-handle = <&mdio0_phy14>;
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};
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&dpmac12 {
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phy-handle = <&mdio0_phy15>;
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};
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