90 lines
1.4 KiB
Plaintext
90 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for NXP LS1012A 2G5RDB Board.
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*
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* Copyright 2017 NXP
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*
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* Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
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*/
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/dts-v1/;
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#include "fsl-ls1012a.dtsi"
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/ {
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model = "LS1012A 2G5RDB Board";
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compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
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aliases {
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ethernet0 = &pfe_mac0;
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ethernet1 = &pfe_mac1;
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};
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};
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&duart0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&qspi {
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num-cs = <2>;
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bus-num = <0>;
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status = "okay";
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qflash0: s25fs512s@0 {
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compatible = "spansion,m25p80";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <20000000>;
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m25p,fast-read;
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reg = <0>;
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};
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};
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&sata {
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status = "okay";
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};
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&pfe {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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pfe_mac0: ethernet@0 {
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compatible = "fsl,pfe-gemac-port";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>; /* GEM_ID */
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fsl,mdio-mux-val = <0x0>;
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phy-mode = "sgmii-2500";
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phy-handle = <&sgmii_phy1>;
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};
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pfe_mac1: ethernet@1 {
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compatible = "fsl,pfe-gemac-port";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1>; /* GEM_ID */
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fsl,mdio-mux-val = <0x0>;
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phy-mode = "sgmii-2500";
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phy-handle = <&sgmii_phy2>;
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};
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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sgmii_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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sgmii_phy2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x2>;
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};
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};
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};
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