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The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15 cores (in a 4x4 cluster configuration). The cores within each cluster share an L2 cache, and the clusters are connected to each other via a CCN-504 cache coherent interconnect. This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located above 4GB in the memory map. Signed-off-by: Anders Berg <anders.berg@lsi.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
13 lines
270 B
Plaintext
13 lines
270 B
Plaintext
Axxia AXM55xx device tree bindings
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Boards using the AXM55xx SoC need to have the following properties:
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Required root node property:
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- compatible = "lsi,axm5516"
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Boards:
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LSI AXM5516 Validation board (Amarillo)
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compatible = "lsi,axm5516-amarillo", "lsi,axm5516"
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