James Morse 1b568dfec3 arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419 ... [ Upstream commit 05460849c3b51180d5ada3373d0449aea19075e4 ] Cores affected by Neoverse-N1 #1542419 could execute a stale instruction when a branch is updated to point to freshly generated instructions. To workaround this issue we need user-space to issue unnecessary icache maintenance that we can trap. Start by hiding CTR_EL0.DIC. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> [ Removed cpu_enable_trap_ctr_access() hunk due to no 4afe8e79da] Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2020-04-29 16:31:08 +02:00
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acpi_object_usage.txt	ARM64: ACPI: Update documentation for latest specification version	2016-06-21 16:26:09 +01:00
arm-acpi.txt	ARM64: ACPI: Update documentation for latest specification version	2016-06-21 16:26:09 +01:00
booting.txt	arm64: add the initrd region to the linear mapping explicitly	2016-04-14 16:20:45 +01:00
cpu-feature-registers.txt	arm64: Expose Arm v8.4 features	2018-03-19 18:14:27 +00:00
elf_hwcaps.txt	arm64: docs: Document SSBS HWCAP	2019-10-11 18:21:31 +02:00
legacy_instructions.txt	arm64: Emulate SETEND for AArch32 tasks	2015-01-23 17:11:44 +00:00
memory.txt	arm64: KVM: Allow mapping of vectors outside of the RAM region	2018-03-19 13:06:46 +00:00
silicon-errata.txt	arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419	2020-04-29 16:31:08 +02:00
sve.txt	Documentation/arm64/sve: Couple of improvements and typos	2018-08-29 11:33:19 +01:00
tagged-pointers.txt	arm64: documentation: document tagged pointer stack constraints	2017-05-09 17:43:18 +01:00