568 lines
16 KiB
C
568 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* DRM driver for Ilitek ILI9805 panels on Sharp Brain
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*
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* Copyright 2020 Takumi Sueda <puhitaku@gmail.com>
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*
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* Based on ili9341.c
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* Copyright 2018 David Lechner <david@lechnology.com>
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*
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* Based on mi0283qt.c:
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* Copyright 2016 Noralf Trønnes
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*/
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#include <linux/backlight.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/gpio/consumer.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_damage_helper.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_mipi_dbi.h>
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#include <drm/drm_modeset_helper.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_vblank.h>
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#include <video/mipi_display.h>
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#include "mxsfb_regs.h"
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#define RESET_TIMEOUT 1000000
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#define TX_TIMEOUT 1000000
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#define ILI9805_MADCTL_GS BIT(0)
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#define ILI9805_MADCTL_BGR BIT(3)
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#define ILI9805_MADCTL_MV BIT(5)
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#define ILI9805_MADCTL_MX BIT(6)
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#define ILI9805_MADCTL_MY BIT(7)
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struct brain_drm_private {
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void __iomem *base;
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struct platform_device *pdev;
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struct clk *clk_lcdif;
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bool enabled;
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struct drm_simple_display_pipe pipe;
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const struct drm_display_mode *mode;
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struct drm_connector connector;
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struct drm_panel *panel;
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};
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static const struct {
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u8 payload;
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u8 data;
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u32 delay;
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} lcd_regs[] = {
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{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
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{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
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{ 0xfd, 0, 0 }, /* PFM Type C */
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{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
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{ 0xf8, 0, 0 }, /* PFM Type C */
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{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
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{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
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{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
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{ 0x72, 1, 0 },
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{ 0xf1, 0, 0 }, /* Gate Modulation */
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{ 0x00, 1, 0 },
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{ 0xf2, 0, 0 }, /* CR/EQ/PC */
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{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
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{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
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{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
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{ 0xeb, 0, 0 }, /* ? */
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{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
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{ 0xe0, 0, 0 }, /* Positive Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
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{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
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{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xe1, 0, 0 }, /* Negative Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
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{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xc1, 0, 0 }, /* Power Control 1 */
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{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
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{ 0xc7, 0, 0 }, /* VCOM Control */
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{ 0x90, 1, 0 },
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{ 0xb1, 0, 0 }, /* Frame Rate Control */
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{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
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{ 0xb4, 0, 0 }, /* Display Inversion Control */
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{ 0x02, 1, 0 },
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{ 0xbb, 0, 0 }, /* ? */
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{ 0x14, 1, 0 }, { 0x55, 1, 0 },
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{ 0x36, 0, 0 }, /* Memory Access Control */
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{ 0x28, 1, 0 },
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{ 0x3a, 0, 0 }, /* Interface Pixel Format */
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{ 0x55, 1, 0 },
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{ 0x21, 0, 0 }, /* Display Inversion On */
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{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
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{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
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{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 },
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{ 0x35, 0, 0 }, /* Tearing Effect Line On */
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{ 0x00, 1, 0 },
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{ 0x11, 0, 120 }, /* Sleep Out */
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{ 0x29, 0, 20 }, /* Display On */
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{ 0x2a, 0, 0 }, /* Column Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
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{ 0x2b, 0, 0 }, /* Page Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
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{ 0x2c, 0, 0 }, /* Memory Write*/
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};
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static struct brain_drm_private *pipe_to_brain_drm_private(struct drm_simple_display_pipe *pipe)
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{
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return container_of(pipe, struct brain_drm_private, pipe);
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}
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static int brain_clear_poll(const void __iomem *addr, u32 mask, u32 timeout)
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{
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u32 reg;
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return readl_poll_timeout(addr, reg, !(reg & mask), 0, timeout);
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}
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static int brain_write_clear_poll(void __iomem *addr, u32 mask, u32 timeout)
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{
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u32 reg;
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writel(mask, addr + REG_CLR);
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return readl_poll_timeout(addr, reg, !(reg & mask), 0, timeout);
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}
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static int brain_write_byte(struct brain_drm_private *priv, u8 payload, const u8 is_data)
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{
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if (brain_clear_poll(priv->base + LCDC_CTRL, CTRL_RUN, TX_TIMEOUT)) {
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return -ETIMEDOUT;
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}
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writel(TRANSFER_COUNT_SET_VCOUNT(1) | TRANSFER_COUNT_SET_HCOUNT(1),
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priv->base + LCDC_V4_TRANSFER_COUNT);
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writel(CTRL_DATA_SELECT | CTRL_RUN, priv->base + LCDC_CTRL + REG_CLR);
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if (is_data) {
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writel(CTRL_DATA_SELECT, priv->base + LCDC_CTRL + REG_SET);
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}
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writel(CTRL_RUN, priv->base + LCDC_CTRL + REG_SET);
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if (brain_clear_poll(priv->base + LCDC_STAT, STAT_LFIFO_FULL, TX_TIMEOUT)) {
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return -ETIMEDOUT;
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}
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writel(payload, priv->base + LCDC_DATA);
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if (brain_clear_poll(priv->base + LCDC_CTRL, CTRL_RUN, TX_TIMEOUT)) {
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int brain_reset_block(void __iomem *reset_addr)
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{
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int ret;
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ret = brain_write_clear_poll(reset_addr, CTRL_SFTRST, RESET_TIMEOUT);
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if (ret)
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return ret;
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writel(CTRL_CLKGATE, reset_addr + REG_CLR);
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ret = brain_write_clear_poll(reset_addr, CTRL_SFTRST, RESET_TIMEOUT);
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if (ret)
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return ret;
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return brain_write_clear_poll(reset_addr, CTRL_CLKGATE, RESET_TIMEOUT);
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}
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static int brain_set_pixel_fmt(struct brain_drm_private *ili, struct drm_plane_state *plane_state)
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{
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struct drm_crtc *crtc = &ili->pipe.crtc;
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struct drm_device *drm = crtc->dev;
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const u32 format = plane_state->fb->format->format;
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u32 ctrl, ctrl1;
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ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
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/* CTRL1 contains IRQ config and status bits, preserve those. */
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ctrl1 = readl(ili->base + LCDC_CTRL1);
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ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
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switch (format) {
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case DRM_FORMAT_RGB565:
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dev_dbg(drm->dev, "Setting up RGB565 mode\n");
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ctrl |= CTRL_SET_WORD_LENGTH(0);
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ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
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break;
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case DRM_FORMAT_XRGB8888:
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dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");
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ctrl |= CTRL_SET_WORD_LENGTH(3);
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/* Do not use packed pixels = one pixel per word instead. */
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ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
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break;
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default:
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dev_err(drm->dev, "Unhandled pixel format %08x\n", format);
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return -EINVAL;
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}
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writel(ctrl1, ili->base + LCDC_CTRL1);
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writel(ctrl, ili->base + LCDC_CTRL);
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return 0;
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}
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static void brain_set_bus_fmt(struct brain_drm_private *ili)
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{
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struct drm_crtc *crtc = &ili->pipe.crtc;
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struct drm_device *drm = crtc->dev;
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u32 bus_format = MEDIA_BUS_FMT_RGB565_1X16;
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u32 reg;
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reg = readl(ili->base + LCDC_CTRL);
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if (ili->connector.display_info.num_bus_formats)
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bus_format = ili->connector.display_info.bus_formats[0];
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reg &= ~CTRL_BUS_WIDTH_MASK;
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switch (bus_format) {
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case MEDIA_BUS_FMT_RGB565_1X16:
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reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
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break;
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case MEDIA_BUS_FMT_RGB666_1X18:
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reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
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break;
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case MEDIA_BUS_FMT_RGB888_1X24:
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reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
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break;
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default:
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dev_err(drm->dev, "Unknown media bus format %d\n", bus_format);
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break;
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}
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writel(reg, ili->base + LCDC_CTRL);
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}
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static void brain_enable(struct drm_simple_display_pipe *pipe,
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struct drm_crtc_state *crtc_state,
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struct drm_plane_state *plane_state)
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{
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struct brain_drm_private *ili;
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struct drm_display_mode *m = &crtc_state->adjusted_mode;
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int i, ret, idx;
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u32 valid;
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ili = pipe_to_brain_drm_private(pipe);
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m = &ili->pipe.crtc.state->adjusted_mode;
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if (!drm_dev_enter(pipe->crtc.dev, &idx))
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return;
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clk_prepare_enable(ili->clk_lcdif);
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ret = brain_reset_block(ili->base);
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if (ret)
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return;
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writel(CTRL1_FIFO_CLEAR, ili->base + LCDC_CTRL1 + REG_SET);
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ret = brain_set_pixel_fmt(ili, plane_state);
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if (ret)
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return;
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/* Unset DOTCLK */
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writel(CTRL_MASTER | CTRL_DOTCLK_MODE | CTRL_BYPASS_COUNT, ili->base + LCDC_CTRL + REG_CLR);
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brain_set_bus_fmt(ili);
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/* Timing */
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writel(TIMING_CMD_HOLD(1) | TIMING_CMD_SETUP(1) | TIMING_DATA_HOLD(1) | TIMING_DATA_SETUP(1),
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ili->base + LCDC_TIMING);
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/* Initialize LCD */
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/* Decrease the bus width to 8-bit temporarily */
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valid = CTRL1_GET_BYTE_PACKAGING(readl(ili->base + LCDC_CTRL1));
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writel(CTRL1_SET_BYTE_PACKAGING(0xf), ili->base + LCDC_CTRL1 + REG_CLR);
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writel(CTRL1_SET_BYTE_PACKAGING(0x3), ili->base + LCDC_CTRL1 + REG_SET);
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for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
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brain_write_byte(ili, lcd_regs[i].payload, lcd_regs[i].data);
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mdelay(lcd_regs[i].delay);
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}
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writel(CTRL1_SET_BYTE_PACKAGING(0xf), ili->base + LCDC_CTRL1 + REG_CLR);
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writel(CTRL1_SET_BYTE_PACKAGING(valid), ili->base + LCDC_CTRL1 + REG_SET);
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/* Ready to transmit */
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writel(CTRL_MASTER, ili->base + LCDC_CTRL + REG_SET);
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ili->enabled = true;
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}
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static void brain_disable(struct drm_simple_display_pipe *pipe)
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{
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struct brain_drm_private *ili = pipe_to_brain_drm_private(pipe);
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clk_disable_unprepare(ili->clk_lcdif);
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return;
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}
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static void brain_fb_dirty_full(struct brain_drm_private *ili, struct drm_framebuffer *fb, struct drm_rect *rect) {
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struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
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int idx;
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u16 width = fb->width;
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u16 height = fb->height;
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if (!ili->enabled)
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return;
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if (!drm_dev_enter(fb->dev, &idx))
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return;
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if (brain_clear_poll(ili->base + LCDC_CTRL, CTRL_RUN, TX_TIMEOUT)) {
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dev_warn(&ili->pdev->dev, "Exceeded timeout\n");
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goto timeout_exit;
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}
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writel(cma_obj->paddr, ili->base + LCDC_V4_CUR_BUF);
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writel(cma_obj->paddr, ili->base + LCDC_V4_NEXT_BUF);
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writel(TRANSFER_COUNT_SET_VCOUNT(height) | TRANSFER_COUNT_SET_HCOUNT(width),
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ili->base + LCDC_V4_TRANSFER_COUNT);
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writel(CTRL_DATA_SELECT | CTRL_RUN, ili->base + LCDC_CTRL + REG_SET);
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timeout_exit:
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drm_dev_exit(idx);
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}
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static void brain_update(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *old_state)
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{
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struct brain_drm_private *ili = pipe_to_brain_drm_private(pipe);
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struct drm_plane_state *state = pipe->plane.state;
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_rect rect;
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if (drm_atomic_helper_damage_merged(old_state, state, &rect))
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brain_fb_dirty_full(ili, state->fb, &rect);
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if (crtc->state->event) {
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spin_lock_irq(&crtc->dev->event_lock);
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drm_crtc_send_vblank_event(crtc, crtc->state->event);
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spin_unlock_irq(&crtc->dev->event_lock);
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crtc->state->event = NULL;
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}
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}
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static const struct drm_simple_display_pipe_funcs brain_pipe_funcs = {
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.enable = brain_enable,
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.disable = brain_disable,
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.update = brain_update,
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.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
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};
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static const struct drm_display_mode brainlcd_mode = {
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DRM_SIMPLE_MODE(800, 480, 112, 67),
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};
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DEFINE_DRM_GEM_CMA_FOPS(brain_fops);
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static int brain_connector_get_modes(struct drm_connector *connector)
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{
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struct drm_display_mode *mode;
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mode = drm_mode_duplicate(connector->dev, &brainlcd_mode);
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if (!mode) {
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DRM_ERROR("Failed to duplicate mode\n");
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return 0;
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}
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if (mode->name[0] == '\0')
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drm_mode_set_name(mode);
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mode->type |= DRM_MODE_TYPE_PREFERRED;
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drm_mode_probed_add(connector, mode);
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if (mode->width_mm) {
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connector->display_info.width_mm = mode->width_mm;
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connector->display_info.height_mm = mode->height_mm;
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}
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return 1;
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}
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static const struct drm_connector_helper_funcs brain_connector_helper_funcs = {
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.get_modes = brain_connector_get_modes,
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};
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static const struct drm_connector_funcs brain_connector_funcs = {
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.reset = drm_atomic_helper_connector_reset,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = drm_connector_cleanup,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static const struct drm_mode_config_funcs brain_mode_config_funcs = {
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.fb_create = drm_gem_fb_create_with_dirty,
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = drm_atomic_helper_commit,
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};
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static struct drm_driver brain_driver = {
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.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
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.fops = &brain_fops,
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DRM_GEM_CMA_VMAP_DRIVER_OPS,
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.name = "brain",
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.desc = "Ilitek ILI9805",
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.date = "20200829",
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.major = 1,
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.minor = 0,
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};
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static const struct of_device_id brain_of_match[] = {
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{ .compatible = "sharp,brainlcd" },
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{},
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};
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MODULE_DEVICE_TABLE(of, brain_of_match);
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static int brain_probe(struct platform_device *pdev)
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{
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|
struct drm_device *drm;
|
|
struct brain_drm_private *ili;
|
|
size_t bufsize;
|
|
struct resource *res;
|
|
struct gpio_desc *en;
|
|
int i, ret;
|
|
|
|
const struct of_device_id *of_id =
|
|
of_match_device(brain_of_match, &pdev->dev);
|
|
|
|
static const uint32_t formats[] = {
|
|
DRM_FORMAT_RGB565,
|
|
};
|
|
|
|
if (!pdev->dev.of_node)
|
|
return -ENODEV;
|
|
|
|
if (of_id)
|
|
pdev->id_entry = of_id->data;
|
|
|
|
drm = drm_dev_alloc(&brain_driver, &pdev->dev);
|
|
if (IS_ERR(drm))
|
|
return PTR_ERR(drm);
|
|
|
|
ili = devm_kzalloc(&pdev->dev, sizeof(*ili), GFP_KERNEL);
|
|
if (!ili) {
|
|
drm_dev_put(drm);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ili->pdev = pdev;
|
|
drm->dev_private = ili;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
ili->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(ili->base)) {
|
|
drm_dev_put(drm);
|
|
return PTR_ERR(ili->base);
|
|
}
|
|
|
|
ili->enabled = false;
|
|
|
|
ili->clk_lcdif = devm_clk_get(drm->dev, NULL);
|
|
if (IS_ERR(ili->clk_lcdif)) {
|
|
drm_dev_put(drm);
|
|
return PTR_ERR(ili->clk_lcdif);
|
|
}
|
|
|
|
drm_mode_config_init(drm);
|
|
drm->mode_config.funcs = &brain_mode_config_funcs;
|
|
|
|
for (i = 0; i < gpiod_count(&pdev->dev, "sharp,en"); i++) {
|
|
en = devm_gpiod_get_index(&pdev->dev, "sharp,en", i, GPIOD_OUT_HIGH);
|
|
if (IS_ERR(en))
|
|
dev_err(&pdev->dev, "failed to get gpio %d\n", i);
|
|
continue;
|
|
ret = gpiod_direction_output(en, 1);
|
|
if (IS_ERR(en))
|
|
dev_err(&pdev->dev, "failed to output gpio %d\n", i);
|
|
}
|
|
|
|
bufsize = brainlcd_mode.vdisplay * brainlcd_mode.hdisplay * sizeof(u16);
|
|
|
|
ili->mode = &brainlcd_mode;
|
|
drm->mode_config.min_width = brainlcd_mode.hdisplay;
|
|
drm->mode_config.max_width = brainlcd_mode.hdisplay;
|
|
drm->mode_config.min_height = brainlcd_mode.vdisplay;
|
|
drm->mode_config.max_height = brainlcd_mode.vdisplay;
|
|
|
|
drm_connector_helper_add(&ili->connector, &brain_connector_helper_funcs);
|
|
ret = drm_connector_init(drm, &ili->connector, &brain_connector_funcs, DRM_MODE_CONNECTOR_DPI);
|
|
if (ret) {
|
|
drm_dev_put(drm);
|
|
return ret;
|
|
}
|
|
|
|
ret = drm_simple_display_pipe_init(drm, &ili->pipe, &brain_pipe_funcs,
|
|
formats, ARRAY_SIZE(formats),
|
|
NULL, &ili->connector);
|
|
if (ret) {
|
|
drm_dev_put(drm);
|
|
return ret;
|
|
}
|
|
|
|
drm_mode_config_reset(drm);
|
|
|
|
ret = drm_dev_register(drm, 0);
|
|
if (ret) {
|
|
drm_dev_put(drm);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, drm);
|
|
drm_fbdev_generic_setup(drm, 16);
|
|
return 0;
|
|
}
|
|
|
|
static int brain_remove(struct platform_device *pdev)
|
|
{
|
|
struct drm_device *drm = platform_get_drvdata(pdev);
|
|
|
|
drm_dev_unplug(drm);
|
|
drm_atomic_helper_shutdown(drm);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void brain_shutdown(struct platform_device *pdev)
|
|
{
|
|
drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
|
|
}
|
|
|
|
static struct platform_driver brain_platform_driver = {
|
|
.probe = brain_probe,
|
|
.remove = brain_remove,
|
|
.shutdown = brain_shutdown,
|
|
.driver = {
|
|
.name = "brain",
|
|
.of_match_table = brain_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(brain_platform_driver);
|
|
|
|
MODULE_DESCRIPTION("DRM driver for Ilitek ILI9805 panels on Sharp Brain");
|
|
MODULE_AUTHOR("Takumi Sueda <puhitaku@gmail.com>");
|
|
MODULE_LICENSE("GPL");
|