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63104eec23
include/linux/version.h contained both actual KERNEL version and UTS_RELEASE that contains a subset from git SHA1 for when kernel was compiled as part of a git repository. This had the unfortunate side-effect that all files including version.h would be recompiled when some git changes was made due to changes SHA1. Split it out so we keep independent parts in separate files. Also update checkversion.pl script to no longer check for UTS_RELEASE. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
549 lines
13 KiB
C
549 lines
13 KiB
C
/*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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*/
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/*
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* bootup setup stuff..
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/a.out.h>
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#include <linux/tty.h>
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#include <linux/major.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/utsrelease.h>
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#include <linux/adb.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/ide.h>
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#include <linux/console.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/timer.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/prom.h>
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#include <asm/gg2.h>
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#include <asm/pci-bridge.h>
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#include <asm/dma.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/hydra.h>
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#include <asm/sections.h>
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#include <asm/time.h>
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#include <asm/i8259.h>
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#include <asm/mpic.h>
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#include <asm/rtas.h>
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#include <asm/xmon.h>
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#include "chrp.h"
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void rtas_indicator_progress(char *, unsigned short);
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int _chrp_type;
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EXPORT_SYMBOL(_chrp_type);
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struct mpic *chrp_mpic;
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/* Used for doing CHRP event-scans */
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DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
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unsigned long event_scan_interval;
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/*
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* XXX this should be in xmon.h, but putting it there means xmon.h
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* has to include <linux/interrupt.h> (to get irqreturn_t), which
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* causes all sorts of problems. -- paulus
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*/
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extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
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extern unsigned long loops_per_jiffy;
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#ifdef CONFIG_SMP
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extern struct smp_ops_t chrp_smp_ops;
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#endif
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static const char *gg2_memtypes[4] = {
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"FPM", "SDRAM", "EDO", "BEDO"
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};
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static const char *gg2_cachesizes[4] = {
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"256 KB", "512 KB", "1 MB", "Reserved"
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};
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static const char *gg2_cachetypes[4] = {
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"Asynchronous", "Reserved", "Flow-Through Synchronous",
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"Pipelined Synchronous"
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};
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static const char *gg2_cachemodes[4] = {
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"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
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};
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void chrp_show_cpuinfo(struct seq_file *m)
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{
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int i, sdramen;
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unsigned int t;
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struct device_node *root;
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const char *model = "";
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root = find_path_device("/");
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if (root)
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model = get_property(root, "model", NULL);
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seq_printf(m, "machine\t\t: CHRP %s\n", model);
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/* longtrail (goldengate) stuff */
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if (!strncmp(model, "IBM,LongTrail", 13)) {
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/* VLSI VAS96011/12 `Golden Gate 2' */
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/* Memory banks */
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sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
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>>31) & 1;
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for (i = 0; i < (sdramen ? 4 : 6); i++) {
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t = in_le32(gg2_pci_config_base+
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GG2_PCI_DRAM_BANK0+
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i*4);
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if (!(t & 1))
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continue;
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switch ((t>>8) & 0x1f) {
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case 0x1f:
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model = "4 MB";
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break;
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case 0x1e:
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model = "8 MB";
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break;
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case 0x1c:
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model = "16 MB";
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break;
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case 0x18:
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model = "32 MB";
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break;
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case 0x10:
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model = "64 MB";
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break;
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case 0x00:
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model = "128 MB";
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break;
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default:
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model = "Reserved";
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break;
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}
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seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
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gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
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}
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/* L2 cache */
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t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
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seq_printf(m, "board l2\t: %s %s (%s)\n",
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gg2_cachesizes[(t>>7) & 3],
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gg2_cachetypes[(t>>2) & 3],
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gg2_cachemodes[t & 3]);
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}
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}
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/*
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* Fixes for the National Semiconductor PC78308VUL SuperI/O
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*
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* Some versions of Open Firmware incorrectly initialize the IRQ settings
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* for keyboard and mouse
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*/
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static inline void __init sio_write(u8 val, u8 index)
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{
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outb(index, 0x15c);
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outb(val, 0x15d);
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}
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static inline u8 __init sio_read(u8 index)
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{
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outb(index, 0x15c);
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return inb(0x15d);
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}
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static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
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u8 type)
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{
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u8 level0, type0, active;
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/* select logical device */
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sio_write(device, 0x07);
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active = sio_read(0x30);
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level0 = sio_read(0x70);
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type0 = sio_read(0x71);
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if (level0 != level || type0 != type || !active) {
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printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
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"remapping to level %d, type %d, active\n",
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name, level0, type0, !active ? "in" : "", level, type);
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sio_write(0x01, 0x30);
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sio_write(level, 0x70);
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sio_write(type, 0x71);
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}
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}
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static void __init sio_init(void)
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{
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struct device_node *root;
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if ((root = find_path_device("/")) &&
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!strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
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/* logical device 0 (KBC/Keyboard) */
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sio_fixup_irq("keyboard", 0, 1, 2);
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/* select logical device 1 (KBC/Mouse) */
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sio_fixup_irq("mouse", 1, 12, 2);
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}
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}
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static void __init pegasos_set_l2cr(void)
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{
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struct device_node *np;
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/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
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if (_chrp_type != _CHRP_Pegasos)
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return;
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/* Enable L2 cache if needed */
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np = find_type_devices("cpu");
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if (np != NULL) {
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unsigned int *l2cr = (unsigned int *)
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get_property (np, "l2cr", NULL);
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if (l2cr == NULL) {
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printk ("Pegasos l2cr : no cpu l2cr property found\n");
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return;
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}
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if (!((*l2cr) & 0x80000000)) {
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printk ("Pegasos l2cr : L2 cache was not active, "
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"activating\n");
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_set_L2CR(0);
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_set_L2CR((*l2cr) | 0x80000000);
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}
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}
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}
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void __init chrp_setup_arch(void)
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{
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struct device_node *root = find_path_device ("/");
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char *machine = NULL;
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000/HZ;
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if (root)
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machine = get_property(root, "model", NULL);
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if (machine && strncmp(machine, "Pegasos", 7) == 0) {
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_chrp_type = _CHRP_Pegasos;
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} else if (machine && strncmp(machine, "IBM", 3) == 0) {
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_chrp_type = _CHRP_IBM;
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} else if (machine && strncmp(machine, "MOT", 3) == 0) {
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_chrp_type = _CHRP_Motorola;
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} else {
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/* Let's assume it is an IBM chrp if all else fails */
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_chrp_type = _CHRP_IBM;
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}
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printk("chrp type = %x\n", _chrp_type);
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rtas_initialize();
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if (rtas_token("display-character") >= 0)
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ppc_md.progress = rtas_progress;
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/* use RTAS time-of-day routines if available */
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if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
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ppc_md.get_boot_time = rtas_get_boot_time;
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ppc_md.get_rtc_time = rtas_get_rtc_time;
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ppc_md.set_rtc_time = rtas_set_rtc_time;
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}
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#ifdef CONFIG_BLK_DEV_INITRD
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/* this is fine for chrp */
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initrd_below_start_ok = 1;
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
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/* On pegasos, enable the L2 cache if not already done by OF */
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pegasos_set_l2cr();
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/* Lookup PCI host bridges */
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chrp_find_bridges();
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/*
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* Temporary fixes for PCI devices.
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* -- Geert
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*/
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hydra_init(); /* Mac I/O */
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/*
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* Fix the Super I/O configuration
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*/
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sio_init();
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pci_create_OF_bus_map();
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#ifdef CONFIG_SMP
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smp_ops = &chrp_smp_ops;
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#endif /* CONFIG_SMP */
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/*
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* Print the banner, then scroll down so boot progress
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* can be printed. -- Cort
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*/
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if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
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}
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void
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chrp_event_scan(unsigned long unused)
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{
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unsigned char log[1024];
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int ret = 0;
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/* XXX: we should loop until the hardware says no more error logs -- Cort */
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rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
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__pa(log), 1024);
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mod_timer(&__get_cpu_var(heartbeat_timer),
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jiffies + event_scan_interval);
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}
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/*
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* Finds the open-pic node and sets up the mpic driver.
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*/
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static void __init chrp_find_openpic(void)
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{
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struct device_node *np, *root;
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int len, i, j, irq_count;
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int isu_size, idu_size;
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unsigned int *iranges, *opprop = NULL;
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int oplen = 0;
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unsigned long opaddr;
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int na = 1;
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unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
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np = find_type_devices("open-pic");
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if (np == NULL)
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return;
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root = find_path_device("/");
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if (root) {
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opprop = (unsigned int *) get_property
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(root, "platform-open-pic", &oplen);
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na = prom_n_addr_cells(root);
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}
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if (opprop && oplen >= na * sizeof(unsigned int)) {
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opaddr = opprop[na-1]; /* assume 32-bit */
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oplen /= na * sizeof(unsigned int);
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} else {
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struct resource r;
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if (of_address_to_resource(np, 0, &r))
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return;
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opaddr = r.start;
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oplen = 0;
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}
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printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
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irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
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prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
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/* i8259 cascade is always positive level */
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init_senses[0] = IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE;
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iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
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if (iranges == NULL)
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len = 0; /* non-distributed mpic */
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else
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len /= 2 * sizeof(unsigned int);
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/*
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* The first pair of cells in interrupt-ranges refers to the
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* IDU; subsequent pairs refer to the ISUs.
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*/
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if (oplen < len) {
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printk(KERN_ERR "Insufficient addresses for distributed"
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" OpenPIC (%d < %d)\n", oplen, len);
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len = oplen;
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}
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isu_size = 0;
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idu_size = 0;
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if (len > 0 && iranges[1] != 0) {
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printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
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iranges[0], iranges[0] + iranges[1] - 1);
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idu_size = iranges[1];
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}
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if (len > 1)
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isu_size = iranges[3];
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chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
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isu_size, NUM_ISA_INTERRUPTS, irq_count,
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NR_IRQS - 4, init_senses, irq_count,
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" MPIC ");
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if (chrp_mpic == NULL) {
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printk(KERN_ERR "Failed to allocate MPIC structure\n");
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return;
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}
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j = na - 1;
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for (i = 1; i < len; ++i) {
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iranges += 2;
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j += na;
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printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
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iranges[0], iranges[0] + iranges[1] - 1,
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opprop[j]);
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mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
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}
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mpic_init(chrp_mpic);
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mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
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}
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#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
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static struct irqaction xmon_irqaction = {
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.handler = xmon_irq,
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.mask = CPU_MASK_NONE,
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.name = "XMON break",
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};
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#endif
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void __init chrp_init_IRQ(void)
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{
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struct device_node *np;
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unsigned long chrp_int_ack = 0;
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#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
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struct device_node *kbd;
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#endif
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for (np = find_devices("pci"); np != NULL; np = np->next) {
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unsigned int *addrp = (unsigned int *)
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get_property(np, "8259-interrupt-acknowledge", NULL);
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if (addrp == NULL)
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continue;
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chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
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break;
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}
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if (np == NULL)
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printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
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chrp_find_openpic();
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i8259_init(chrp_int_ack, 0);
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if (_chrp_type == _CHRP_Pegasos)
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ppc_md.get_irq = i8259_irq;
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#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
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/* see if there is a keyboard in the device tree
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with a parent of type "adb" */
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for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
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if (kbd->parent && kbd->parent->type
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&& strcmp(kbd->parent->type, "adb") == 0)
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break;
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if (kbd)
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setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
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#endif
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}
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void __init
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chrp_init2(void)
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{
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struct device_node *device;
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unsigned int *p = NULL;
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#ifdef CONFIG_NVRAM
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chrp_nvram_init();
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#endif
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request_region(0x20,0x20,"pic1");
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request_region(0xa0,0x20,"pic2");
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request_region(0x00,0x20,"dma1");
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request_region(0x40,0x20,"timer");
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request_region(0x80,0x10,"dma page reg");
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request_region(0xc0,0x20,"dma2");
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/* Get the event scan rate for the rtas so we know how
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* often it expects a heartbeat. -- Cort
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*/
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device = find_devices("rtas");
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if (device)
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p = (unsigned int *) get_property
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(device, "rtas-event-scan-rate", NULL);
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if (p && *p) {
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/*
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* Arrange to call chrp_event_scan at least *p times
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* per minute. We use 59 rather than 60 here so that
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* the rate will be slightly higher than the minimum.
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* This all assumes we don't do hotplug CPU on any
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* machine that needs the event scans done.
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*/
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unsigned long interval, offset;
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int cpu, ncpus;
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struct timer_list *timer;
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interval = HZ * 59 / *p;
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offset = HZ;
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ncpus = num_online_cpus();
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|
event_scan_interval = ncpus * interval;
|
|
for (cpu = 0; cpu < ncpus; ++cpu) {
|
|
timer = &per_cpu(heartbeat_timer, cpu);
|
|
setup_timer(timer, chrp_event_scan, 0);
|
|
timer->expires = jiffies + offset;
|
|
add_timer_on(timer, cpu);
|
|
offset += interval;
|
|
}
|
|
printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
|
|
*p, interval);
|
|
}
|
|
|
|
if (ppc_md.progress)
|
|
ppc_md.progress(" Have fun! ", 0x7777);
|
|
}
|
|
|
|
static int __init chrp_probe(void)
|
|
{
|
|
char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
|
|
"device_type", NULL);
|
|
if (dtype == NULL)
|
|
return 0;
|
|
if (strcmp(dtype, "chrp"))
|
|
return 0;
|
|
|
|
ISA_DMA_THRESHOLD = ~0L;
|
|
DMA_MODE_READ = 0x44;
|
|
DMA_MODE_WRITE = 0x48;
|
|
isa_io_base = CHRP_ISA_IO_BASE; /* default value */
|
|
ppc_do_canonicalize_irqs = 1;
|
|
|
|
/* Assume we have an 8259... */
|
|
__irq_offset_value = NUM_ISA_INTERRUPTS;
|
|
|
|
return 1;
|
|
}
|
|
|
|
define_machine(chrp) {
|
|
.name = "CHRP",
|
|
.probe = chrp_probe,
|
|
.setup_arch = chrp_setup_arch,
|
|
.init = chrp_init2,
|
|
.show_cpuinfo = chrp_show_cpuinfo,
|
|
.init_IRQ = chrp_init_IRQ,
|
|
.get_irq = mpic_get_irq,
|
|
.pcibios_fixup = chrp_pcibios_fixup,
|
|
.restart = rtas_restart,
|
|
.power_off = rtas_power_off,
|
|
.halt = rtas_halt,
|
|
.time_init = chrp_time_init,
|
|
.set_rtc_time = chrp_set_rtc_time,
|
|
.get_rtc_time = chrp_get_rtc_time,
|
|
.calibrate_decr = generic_calibrate_decr,
|
|
.phys_mem_access_prot = pci_phys_mem_access_prot,
|
|
};
|