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580a05f9d4
Currently, the num_msi_left means the vector numbers of NIC,
but if the PF supported RoCE, it contains the vector numbers
of NIC and RoCE(Not expected).
This may cause interrupts lost in some case, because of the
NIC module used the vector resources which belongs to RoCE.
This patch adds a new variable num_nic_msi to store the vector
numbers of NIC, and adjust the default TQP numbers and rss_size
according to the value of num_nic_msi.
Fixes: 46a3df9f97 ("net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support")
Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
324 lines
9.4 KiB
C
324 lines
9.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2016-2017 Hisilicon Limited. */
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#ifndef __HCLGEVF_MAIN_H
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#define __HCLGEVF_MAIN_H
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#include <linux/fs.h>
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#include <linux/if_vlan.h>
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#include <linux/types.h>
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#include "hclge_mbx.h"
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#include "hclgevf_cmd.h"
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#include "hnae3.h"
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#define HCLGEVF_MOD_VERSION "1.0"
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#define HCLGEVF_DRIVER_NAME "hclgevf"
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#define HCLGEVF_MAX_VLAN_ID 4095
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#define HCLGEVF_MISC_VECTOR_NUM 0
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#define HCLGEVF_INVALID_VPORT 0xffff
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#define HCLGEVF_GENERAL_TASK_INTERVAL 5
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#define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2
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/* This number in actual depends upon the total number of VFs
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* created by physical function. But the maximum number of
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* possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
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*/
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#define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1)
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#define HCLGEVF_VECTOR_REG_BASE 0x20000
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#define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400
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#define HCLGEVF_VECTOR_REG_OFFSET 0x4
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#define HCLGEVF_VECTOR_VF_OFFSET 0x100000
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/* bar registers for cmdq */
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#define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000
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#define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004
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#define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008
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#define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010
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#define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014
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#define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018
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#define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C
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#define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020
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#define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024
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#define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028
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#define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100
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#define HCLGEVF_CMDQ_INTR_STS_REG 0x27104
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#define HCLGEVF_CMDQ_INTR_EN_REG 0x27108
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#define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C
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/* bar registers for common func */
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#define HCLGEVF_GRO_EN_REG 0x28000
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/* bar registers for rcb */
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#define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
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#define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
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#define HCLGEVF_RING_RX_BD_NUM_REG 0x80008
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#define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C
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#define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014
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#define HCLGEVF_RING_RX_TAIL_REG 0x80018
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#define HCLGEVF_RING_RX_HEAD_REG 0x8001C
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#define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020
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#define HCLGEVF_RING_RX_OFFSET_REG 0x80024
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#define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028
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#define HCLGEVF_RING_RX_STASH_REG 0x80030
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#define HCLGEVF_RING_RX_BD_ERR_REG 0x80034
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#define HCLGEVF_RING_TX_ADDR_L_REG 0x80040
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#define HCLGEVF_RING_TX_ADDR_H_REG 0x80044
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#define HCLGEVF_RING_TX_BD_NUM_REG 0x80048
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#define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C
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#define HCLGEVF_RING_TX_TC_REG 0x80050
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#define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054
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#define HCLGEVF_RING_TX_TAIL_REG 0x80058
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#define HCLGEVF_RING_TX_HEAD_REG 0x8005C
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#define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060
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#define HCLGEVF_RING_TX_OFFSET_REG 0x80064
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#define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068
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#define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070
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#define HCLGEVF_RING_TX_BD_ERR_REG 0x80074
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#define HCLGEVF_RING_EN_REG 0x80090
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/* bar registers for tqp interrupt */
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#define HCLGEVF_TQP_INTR_CTRL_REG 0x20000
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#define HCLGEVF_TQP_INTR_GL0_REG 0x20100
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#define HCLGEVF_TQP_INTR_GL1_REG 0x20200
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#define HCLGEVF_TQP_INTR_GL2_REG 0x20300
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#define HCLGEVF_TQP_INTR_RL_REG 0x20900
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/* Vector0 interrupt CMDQ event source register(RW) */
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#define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100
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/* Vector0 interrupt CMDQ event status register(RO) */
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#define HCLGEVF_VECTOR0_CMDQ_STAT_REG 0x27104
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/* CMDQ register bits for RX event(=MBX event) */
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#define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1
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/* RST register bits for RESET event */
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#define HCLGEVF_VECTOR0_RST_INT_B 2
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#define HCLGEVF_TQP_RESET_TRY_TIMES 10
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/* Reset related Registers */
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#define HCLGEVF_RST_ING 0x20C00
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#define HCLGEVF_FUN_RST_ING_BIT BIT(0)
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#define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5)
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#define HCLGEVF_CORE_RST_ING_BIT BIT(6)
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#define HCLGEVF_IMP_RST_ING_BIT BIT(7)
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#define HCLGEVF_RST_ING_BITS \
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(HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
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HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)
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#define HCLGEVF_VF_RST_ING 0x07008
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#define HCLGEVF_VF_RST_ING_BIT BIT(16)
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#define HCLGEVF_RSS_IND_TBL_SIZE 512
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#define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff
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#define HCLGEVF_RSS_KEY_SIZE 40
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#define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0
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#define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1
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#define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2
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#define HCLGEVF_RSS_HASH_ALGO_MASK 0xf
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#define HCLGEVF_RSS_CFG_TBL_NUM \
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(HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE)
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#define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
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#define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
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#define HCLGEVF_D_PORT_BIT BIT(0)
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#define HCLGEVF_S_PORT_BIT BIT(1)
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#define HCLGEVF_D_IP_BIT BIT(2)
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#define HCLGEVF_S_IP_BIT BIT(3)
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#define HCLGEVF_V_TAG_BIT BIT(4)
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#define HCLGEVF_STATS_TIMER_INTERVAL 36U
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enum hclgevf_evt_cause {
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HCLGEVF_VECTOR0_EVENT_RST,
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HCLGEVF_VECTOR0_EVENT_MBX,
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HCLGEVF_VECTOR0_EVENT_OTHER,
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};
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/* states of hclgevf device & tasks */
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enum hclgevf_states {
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/* device states */
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HCLGEVF_STATE_DOWN,
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HCLGEVF_STATE_DISABLED,
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HCLGEVF_STATE_IRQ_INITED,
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HCLGEVF_STATE_REMOVING,
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HCLGEVF_STATE_NIC_REGISTERED,
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/* task states */
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HCLGEVF_STATE_SERVICE_SCHED,
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HCLGEVF_STATE_RST_SERVICE_SCHED,
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HCLGEVF_STATE_RST_HANDLING,
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HCLGEVF_STATE_MBX_SERVICE_SCHED,
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HCLGEVF_STATE_MBX_HANDLING,
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HCLGEVF_STATE_CMD_DISABLE,
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};
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#define HCLGEVF_MPF_ENBALE 1
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struct hclgevf_mac {
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u8 media_type;
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u8 module_type;
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u8 mac_addr[ETH_ALEN];
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int link;
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u8 duplex;
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u32 speed;
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u64 supported;
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u64 advertising;
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};
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struct hclgevf_hw {
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void __iomem *io_base;
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int num_vec;
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struct hclgevf_cmq cmq;
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struct hclgevf_mac mac;
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void *hdev; /* hchgevf device it is part of */
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};
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/* TQP stats */
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struct hlcgevf_tqp_stats {
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/* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
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u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
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/* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
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u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
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};
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struct hclgevf_tqp {
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struct device *dev; /* device for DMA mapping */
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struct hnae3_queue q;
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struct hlcgevf_tqp_stats tqp_stats;
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u16 index; /* global index in a NIC controller */
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bool alloced;
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};
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struct hclgevf_cfg {
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u8 vmdq_vport_num;
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u8 tc_num;
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u16 tqp_desc_num;
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u16 rx_buf_len;
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u8 phy_addr;
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u8 media_type;
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u8 mac_addr[ETH_ALEN];
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u32 numa_node_map;
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};
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struct hclgevf_rss_tuple_cfg {
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u8 ipv4_tcp_en;
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u8 ipv4_udp_en;
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u8 ipv4_sctp_en;
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u8 ipv4_fragment_en;
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u8 ipv6_tcp_en;
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u8 ipv6_udp_en;
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u8 ipv6_sctp_en;
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u8 ipv6_fragment_en;
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};
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struct hclgevf_rss_cfg {
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u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */
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u32 hash_algo;
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u32 rss_size;
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u8 hw_tc_map;
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u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */
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struct hclgevf_rss_tuple_cfg rss_tuple_sets;
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};
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struct hclgevf_misc_vector {
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u8 __iomem *addr;
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int vector_irq;
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};
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struct hclgevf_rst_stats {
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u32 rst_cnt; /* the number of reset */
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u32 vf_func_rst_cnt; /* the number of VF function reset */
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u32 flr_rst_cnt; /* the number of FLR */
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u32 vf_rst_cnt; /* the number of VF reset */
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u32 rst_done_cnt; /* the number of reset completed */
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u32 hw_rst_done_cnt; /* the number of HW reset completed */
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u32 rst_fail_cnt; /* the number of VF reset fail */
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};
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struct hclgevf_dev {
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struct pci_dev *pdev;
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struct hnae3_ae_dev *ae_dev;
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struct hclgevf_hw hw;
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struct hclgevf_misc_vector misc_vector;
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struct hclgevf_rss_cfg rss_cfg;
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unsigned long state;
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unsigned long flr_state;
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unsigned long default_reset_request;
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unsigned long last_reset_time;
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enum hnae3_reset_type reset_level;
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unsigned long reset_pending;
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enum hnae3_reset_type reset_type;
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#define HCLGEVF_RESET_REQUESTED 0
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#define HCLGEVF_RESET_PENDING 1
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unsigned long reset_state; /* requested, pending */
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struct hclgevf_rst_stats rst_stats;
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u32 reset_attempts;
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u32 fw_version;
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u16 num_tqps; /* num task queue pairs of this PF */
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u16 alloc_rss_size; /* allocated RSS task queue */
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u16 rss_size_max; /* HW defined max RSS task queue */
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u16 num_alloc_vport; /* num vports this driver supports */
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u32 numa_node_mask;
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u16 rx_buf_len;
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u16 num_tx_desc; /* desc num of per tx queue */
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u16 num_rx_desc; /* desc num of per rx queue */
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u8 hw_tc_map;
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u16 num_msi;
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u16 num_msi_left;
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u16 num_msi_used;
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u16 num_nic_msix; /* Num of nic vectors for this VF */
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u16 num_roce_msix; /* Num of roce vectors for this VF */
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u16 roce_base_msix_offset;
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int roce_base_vector;
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u32 base_msi_vector;
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u16 *vector_status;
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int *vector_irq;
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unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
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bool mbx_event_pending;
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struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
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struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
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struct timer_list service_timer;
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struct timer_list keep_alive_timer;
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struct work_struct service_task;
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struct work_struct keep_alive_task;
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struct work_struct rst_service_task;
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struct work_struct mbx_service_task;
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struct hclgevf_tqp *htqp;
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struct hnae3_handle nic;
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struct hnae3_handle roce;
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struct hnae3_client *nic_client;
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struct hnae3_client *roce_client;
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u32 flag;
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u32 stats_timer;
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};
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static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
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{
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return !!hdev->reset_pending;
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}
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int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode,
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const u8 *msg_data, u8 msg_len, bool need_resp,
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u8 *resp_data, u16 resp_len);
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void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
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void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
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void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
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void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
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u8 duplex);
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void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
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void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
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void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
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u8 *port_base_vlan_info, u8 data_size);
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#endif
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