559 lines
12 KiB
Plaintext
Executable File
559 lines
12 KiB
Plaintext
Executable File
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pads-imx8qm.h>
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#include <dt-bindings/soc/imx8_hsio.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec1;
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ethernet1 = &fec2;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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serial0 = &lpuart0;
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serial1 = &lpuart1;
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serial2 = &lpuart2;
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serial3 = &lpuart3;
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serial4 = &lpuart4;
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isi0 = &isi_0;
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isi1 = &isi_1;
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isi2 = &isi_2;
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isi3 = &isi_3;
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isi4 = &isi_4;
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isi5 = &isi_5;
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isi6 = &isi_6;
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isi7 = &isi_7;
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csi0 = &mipi_csi_0;
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csi1 = &mipi_csi_1;
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mu1 = &lsio_mu1;
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can0 = &flexcan1;
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can1 = &flexcan2;
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can2 = &flexcan3;
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dpu0 = &dpu1;
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dpu1 = &dpu2;
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ldb0 = &ldb1;
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ldb1 = &ldb2;
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i2c0 = &i2c_rpbus_0;
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i2c1 = &i2c_rpbus_1;
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dphy0 = &mipi0_dphy;
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dphy1 = &mipi1_dphy;
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mipi_dsi0 = &mipi0_dsi_host;
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mipi_dsi1 = &mipi1_dsi_host;
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};
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cpus: cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&A53_0>;
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};
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core1 {
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cpu = <&A53_1>;
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};
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core2 {
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cpu = <&A53_2>;
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};
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core3 {
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cpu = <&A53_3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&A72_0>;
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};
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core1 {
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cpu = <&A72_1>;
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};
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};
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};
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A53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A72_0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x0 0x100>;
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clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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next-level-cache = <&A72_L2>;
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operating-points-v2 = <&a72_opp_table>;
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#cooling-cells = <2>;
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};
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A72_1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x0 0x101>;
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clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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next-level-cache = <&A72_L2>;
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operating-points-v2 = <&a72_opp_table>;
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#cooling-cells = <2>;
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};
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A53_L2: l2-cache0 {
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compatible = "cache";
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};
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A72_L2: l2-cache1 {
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compatible = "cache";
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};
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};
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a53_opp_table: a53-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <900000>;
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clock-latency-ns = <150000>;
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};
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opp-896000000 {
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opp-hz = /bits/ 64 <896000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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};
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opp-1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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};
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a72_opp_table: a72-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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};
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opp-1296000000 {
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opp-hz = /bits/ 64 <1296000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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};
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opp-1596000000 {
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opp-hz = /bits/ 64 <1596000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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};
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gic: interrupt-controller@51a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
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<0x0 0x51b00000 0 0xC0000>, /* GICR */
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<0x0 0x52000000 0 0x2000>, /* GICC */
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<0x0 0x52010000 0 0x1000>, /* GICH */
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<0x0 0x52020000 0 0x20000>; /* GICV */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
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};
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clk_dummy: clock-dummy {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "clk_dummy";
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};
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xtal32k: clock-xtal32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xtal_32KHz";
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};
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xtal24m: clock-xtal24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xtal_24MHz";
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};
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smmu: iommu@51400000 {
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compatible = "arm,mmu-500";
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interrupt-parent = <&gic>;
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reg = <0 0x51400000 0 0x40000>;
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#global-interrupts = <1>;
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#iommu-cells = <2>;
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interrupts = <0 32 4>,
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<0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
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<0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
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<0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
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<0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
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<0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
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<0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
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<0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
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<0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
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};
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scu {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3",
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"gip3";
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 0 1
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&lsio_mu1 0 2
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&lsio_mu1 0 3
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&lsio_mu1 1 0
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&lsio_mu1 1 1
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&lsio_mu1 1 2
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&lsio_mu1 1 3
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&lsio_mu1 3 3>;
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pd: imx8qx-pd {
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compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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wakeup-irq = <235 236 237 258 262 267 271
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345 346 347 348>;
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};
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clk: clock-controller {
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compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
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#clock-cells = <2>;
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clocks = <&xtal32k &xtal24m>;
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clock-names = "xtal_32KHz", "xtal_24Mhz";
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};
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iomuxc: pinctrl {
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compatible = "fsl,imx8qm-iomuxc";
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};
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ocotp: imx8qm-ocotp {
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compatible = "fsl,imx8qm-scu-ocotp";
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#address-cells = <1>;
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#size-cells = <1>;
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read-only;
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fec_mac0: mac@1c4 {
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reg = <0x1c4 6>;
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};
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fec_mac1: mac@1c6 {
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reg = <0x1c6 6>;
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};
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};
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rtc: rtc {
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compatible = "fsl,imx8qm-sc-rtc";
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};
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watchdog {
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compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt";
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timeout-sec = <60>;
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};
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tsens: thermal-sensor {
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compatible = "fsl,imx8qm-sc-thermal";
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tsens-num = <6>;
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#thermal-sensor-cells = <1>;
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};
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secvio: secvio {
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compatible = "fsl,imx-sc-secvio";
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nvmem = <&ocotp>;
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};
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};
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thermal_zones: thermal-zones {
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cpu-thermal0 {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_A53>;
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trips {
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cpu_alert0: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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cpu-thermal1 {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_A72>;
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trips {
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cpu_alert1: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit1: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert1>;
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cooling-device =
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<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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gpu-thermal0 {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
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trips {
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gpu_alert0: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_crit0: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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gpu-thermal1 {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
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trips {
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gpu_alert1: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_crit1: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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drc-thermal0 {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
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trips {
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drc_alert0: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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drc_crit0: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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rpmsg0: rpmsg0{
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compatible = "fsl,imx8qm-rpmsg";
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/* up to now, the following channels are used in imx rpmsg
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* - tx1/rx1: messages channel.
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* - general interrupt1: remote proc finish re-init rpmsg stack
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* when A core is partition reset.
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*/
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mbox-names = "tx", "rx", "rxdb";
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mboxes = <&lsio_mu5 0 1
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&lsio_mu5 1 1
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&lsio_mu5 3 1>;
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mub-partition = <3>;
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status = "disabled";
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};
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rpmsg1: rpmsg1{
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compatible = "fsl,imx8qm-rpmsg";
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/* up to now, the following channels are used in imx rpmsg
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* - tx1/rx1: messages channel.
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* - general interrupt1: remote proc finish re-init rpmsg stack
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* when A core is partition reset.
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*/
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mbox-names = "tx", "rx", "rxdb";
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mboxes = <&lsio_mu6 0 1
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&lsio_mu6 1 1
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&lsio_mu6 3 1>;
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mub-partition = <4>;
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status = "disabled";
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};
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sc_pwrkey: sc-powerkey {
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compatible = "fsl,imx8-pwrkey";
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linux,keycode = <KEY_POWER>;
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wakeup-source;
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};
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vpu_subsys_dsp: bus@55000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x55000000 0x0 0x55000000 0x1000000>;
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dsp: dsp@556e8000 {
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compatible = "fsl,imx8qm-dsp";
|
|
reg = <0x556e8000 0x88000>;
|
|
clocks = <&clk_dummy>,
|
|
<&clk_dummy>,
|
|
<&clk_dummy>;
|
|
clock-names = "ipg", "ocram", "core";
|
|
fsl,dsp-firmware = "imx/dsp/hifi4.bin";
|
|
power-domains = <&pd IMX_SC_R_MU_13A>,
|
|
<&pd IMX_SC_R_MU_13B>,
|
|
<&pd IMX_SC_R_DSP>,
|
|
<&pd IMX_SC_R_DSP_RAM>;
|
|
memory-region = <&dsp_reserved>;
|
|
fixup-offset = <0x4000000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
/* sorted in register address */
|
|
#include "imx8-ss-security.dtsi"
|
|
#include "imx8-ss-cm41.dtsi"
|
|
#include "imx8-ss-adma.dtsi"
|
|
#include "imx8-ss-conn.dtsi"
|
|
#include "imx8-ss-ddr.dtsi"
|
|
#include "imx8-ss-lsio.dtsi"
|
|
#include "imx8-ss-hsio.dtsi"
|
|
#include "imx8-ss-img.dtsi"
|
|
#include "imx8-ss-dc0.dtsi"
|
|
#include "imx8-ss-dc1.dtsi"
|
|
#include "imx8-ss-gpu0.dtsi"
|
|
#include "imx8-ss-gpu1.dtsi"
|
|
#include "imx8-ss-vpu.dtsi"
|
|
};
|
|
|
|
#include "imx8qm-ss-audio.dtsi"
|
|
#include "imx8qm-ss-dma.dtsi"
|
|
#include "imx8qm-ss-conn.dtsi"
|
|
#include "imx8qm-ss-ddr.dtsi"
|
|
#include "imx8qm-ss-lsio.dtsi"
|
|
#include "imx8qm-ss-hsio.dtsi"
|
|
#include "imx8qm-ss-dc.dtsi"
|
|
#include "imx8qm-ss-lvds.dtsi"
|
|
#include "imx8qm-ss-mipi.dtsi"
|
|
#include "imx8qm-ss-hdmi.dtsi"
|
|
#include "imx8qm-ss-img.dtsi"
|
|
#include "imx8qm-ss-gpu.dtsi"
|