663 lines
15 KiB
C
663 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* bdc_core.c - BRCM BDC USB3.0 device controller core operations
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*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* Author: Ashwini Pahuja
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/moduleparam.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/clk.h>
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#include "bdc.h"
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#include "bdc_dbg.h"
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/* Poll till controller status is not OIP */
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static int poll_oip(struct bdc *bdc, int usec)
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{
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u32 status;
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/* Poll till STS!= OIP */
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while (usec) {
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status = bdc_readl(bdc->regs, BDC_BDCSC);
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if (BDC_CSTS(status) != BDC_OIP) {
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dev_dbg(bdc->dev,
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"poll_oip complete status=%d",
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BDC_CSTS(status));
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return 0;
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}
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udelay(10);
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usec -= 10;
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}
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dev_err(bdc->dev, "Err: operation timedout BDCSC: 0x%08x\n", status);
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return -ETIMEDOUT;
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}
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/* Stop the BDC controller */
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int bdc_stop(struct bdc *bdc)
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{
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int ret;
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u32 temp;
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dev_dbg(bdc->dev, "%s ()\n\n", __func__);
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temp = bdc_readl(bdc->regs, BDC_BDCSC);
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/* Check if BDC is already halted */
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if (BDC_CSTS(temp) == BDC_HLT) {
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dev_vdbg(bdc->dev, "BDC already halted\n");
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return 0;
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}
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temp &= ~BDC_COP_MASK;
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temp |= BDC_COS|BDC_COP_STP;
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bdc_writel(bdc->regs, BDC_BDCSC, temp);
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ret = poll_oip(bdc, BDC_COP_TIMEOUT);
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if (ret)
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dev_err(bdc->dev, "bdc stop operation failed");
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return ret;
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}
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/* Issue a reset to BDC controller */
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int bdc_reset(struct bdc *bdc)
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{
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u32 temp;
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int ret;
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dev_dbg(bdc->dev, "%s ()\n", __func__);
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/* First halt the controller */
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ret = bdc_stop(bdc);
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if (ret)
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return ret;
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temp = bdc_readl(bdc->regs, BDC_BDCSC);
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temp &= ~BDC_COP_MASK;
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temp |= BDC_COS|BDC_COP_RST;
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bdc_writel(bdc->regs, BDC_BDCSC, temp);
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ret = poll_oip(bdc, BDC_COP_TIMEOUT);
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if (ret)
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dev_err(bdc->dev, "bdc reset operation failed");
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return ret;
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}
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/* Run the BDC controller */
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int bdc_run(struct bdc *bdc)
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{
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u32 temp;
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int ret;
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dev_dbg(bdc->dev, "%s ()\n", __func__);
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temp = bdc_readl(bdc->regs, BDC_BDCSC);
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/* if BDC is already in running state then do not do anything */
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if (BDC_CSTS(temp) == BDC_NOR) {
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dev_warn(bdc->dev, "bdc is already in running state\n");
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return 0;
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}
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temp &= ~BDC_COP_MASK;
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temp |= BDC_COP_RUN;
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temp |= BDC_COS;
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bdc_writel(bdc->regs, BDC_BDCSC, temp);
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ret = poll_oip(bdc, BDC_COP_TIMEOUT);
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if (ret) {
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dev_err(bdc->dev, "bdc run operation failed:%d", ret);
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return ret;
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}
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temp = bdc_readl(bdc->regs, BDC_BDCSC);
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if (BDC_CSTS(temp) != BDC_NOR) {
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dev_err(bdc->dev, "bdc not in normal mode after RUN op :%d\n",
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BDC_CSTS(temp));
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return -ESHUTDOWN;
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}
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return 0;
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}
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/*
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* Present the termination to the host, typically called from upstream port
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* event with Vbus present =1
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*/
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void bdc_softconn(struct bdc *bdc)
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{
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u32 uspc;
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uspc = bdc_readl(bdc->regs, BDC_USPC);
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uspc &= ~BDC_PST_MASK;
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uspc |= BDC_LINK_STATE_RX_DET;
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uspc |= BDC_SWS;
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dev_dbg(bdc->dev, "%s () uspc=%08x\n", __func__, uspc);
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bdc_writel(bdc->regs, BDC_USPC, uspc);
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}
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/* Remove the termination */
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void bdc_softdisconn(struct bdc *bdc)
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{
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u32 uspc;
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uspc = bdc_readl(bdc->regs, BDC_USPC);
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uspc |= BDC_SDC;
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uspc &= ~BDC_SCN;
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dev_dbg(bdc->dev, "%s () uspc=%x\n", __func__, uspc);
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bdc_writel(bdc->regs, BDC_USPC, uspc);
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}
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/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
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static int scratchpad_setup(struct bdc *bdc)
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{
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int sp_buff_size;
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u32 low32;
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u32 upp32;
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sp_buff_size = BDC_SPB(bdc_readl(bdc->regs, BDC_BDCCFG0));
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dev_dbg(bdc->dev, "%s() sp_buff_size=%d\n", __func__, sp_buff_size);
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if (!sp_buff_size) {
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dev_dbg(bdc->dev, "Scratchpad buffer not needed\n");
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return 0;
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}
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/* Refer to BDC spec, Table 4 for description of SPB */
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sp_buff_size = 1 << (sp_buff_size + 5);
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dev_dbg(bdc->dev, "Allocating %d bytes for scratchpad\n", sp_buff_size);
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bdc->scratchpad.buff = dma_alloc_coherent(bdc->dev, sp_buff_size,
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&bdc->scratchpad.sp_dma,
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GFP_KERNEL);
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if (!bdc->scratchpad.buff)
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goto fail;
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bdc->sp_buff_size = sp_buff_size;
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bdc->scratchpad.size = sp_buff_size;
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low32 = lower_32_bits(bdc->scratchpad.sp_dma);
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upp32 = upper_32_bits(bdc->scratchpad.sp_dma);
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cpu_to_le32s(&low32);
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cpu_to_le32s(&upp32);
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bdc_writel(bdc->regs, BDC_SPBBAL, low32);
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bdc_writel(bdc->regs, BDC_SPBBAH, upp32);
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return 0;
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fail:
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bdc->scratchpad.buff = NULL;
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return -ENOMEM;
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}
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/* Allocate the status report ring */
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static int setup_srr(struct bdc *bdc, int interrupter)
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{
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dev_dbg(bdc->dev, "%s() NUM_SR_ENTRIES:%d\n", __func__, NUM_SR_ENTRIES);
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/* Reset the SRR */
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bdc_writel(bdc->regs, BDC_SRRINT(0), BDC_SRR_RWS | BDC_SRR_RST);
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bdc->srr.dqp_index = 0;
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/* allocate the status report descriptors */
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bdc->srr.sr_bds = dma_alloc_coherent(bdc->dev,
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NUM_SR_ENTRIES * sizeof(struct bdc_bd),
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&bdc->srr.dma_addr, GFP_KERNEL);
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if (!bdc->srr.sr_bds)
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return -ENOMEM;
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return 0;
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}
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/* Initialize the HW regs and internal data structures */
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static void bdc_mem_init(struct bdc *bdc, bool reinit)
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{
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u8 size = 0;
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u32 usb2_pm;
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u32 low32;
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u32 upp32;
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u32 temp;
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dev_dbg(bdc->dev, "%s ()\n", __func__);
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bdc->ep0_state = WAIT_FOR_SETUP;
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bdc->dev_addr = 0;
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bdc->srr.eqp_index = 0;
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bdc->srr.dqp_index = 0;
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bdc->zlp_needed = false;
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bdc->delayed_status = false;
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bdc_writel(bdc->regs, BDC_SPBBAL, bdc->scratchpad.sp_dma);
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/* Init the SRR */
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temp = BDC_SRR_RWS | BDC_SRR_RST;
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/* Reset the SRR */
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bdc_writel(bdc->regs, BDC_SRRINT(0), temp);
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dev_dbg(bdc->dev, "bdc->srr.sr_bds =%p\n", bdc->srr.sr_bds);
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temp = lower_32_bits(bdc->srr.dma_addr);
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size = fls(NUM_SR_ENTRIES) - 2;
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temp |= size;
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dev_dbg(bdc->dev, "SRRBAL[0]=%08x NUM_SR_ENTRIES:%d size:%d\n",
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temp, NUM_SR_ENTRIES, size);
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low32 = lower_32_bits(temp);
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upp32 = upper_32_bits(bdc->srr.dma_addr);
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cpu_to_le32s(&low32);
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cpu_to_le32s(&upp32);
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/* Write the dma addresses into regs*/
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bdc_writel(bdc->regs, BDC_SRRBAL(0), low32);
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bdc_writel(bdc->regs, BDC_SRRBAH(0), upp32);
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temp = bdc_readl(bdc->regs, BDC_SRRINT(0));
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temp |= BDC_SRR_IE;
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temp &= ~(BDC_SRR_RST | BDC_SRR_RWS);
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bdc_writel(bdc->regs, BDC_SRRINT(0), temp);
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/* Set the Interrupt Coalescence ~500 usec */
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temp = bdc_readl(bdc->regs, BDC_INTCTLS(0));
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temp &= ~0xffff;
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temp |= INT_CLS;
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bdc_writel(bdc->regs, BDC_INTCTLS(0), temp);
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usb2_pm = bdc_readl(bdc->regs, BDC_USPPM2);
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dev_dbg(bdc->dev, "usb2_pm=%08x", usb2_pm);
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/* Enable hardware LPM Enable */
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usb2_pm |= BDC_HLE;
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bdc_writel(bdc->regs, BDC_USPPM2, usb2_pm);
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/* readback for debug */
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usb2_pm = bdc_readl(bdc->regs, BDC_USPPM2);
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dev_dbg(bdc->dev, "usb2_pm=%08x\n", usb2_pm);
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/* Disable any unwanted SR's on SRR */
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temp = bdc_readl(bdc->regs, BDC_BDCSC);
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/* We don't want Microframe counter wrap SR */
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temp |= BDC_MASK_MCW;
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bdc_writel(bdc->regs, BDC_BDCSC, temp);
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/*
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* In some error cases, driver has to reset the entire BDC controller
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* in that case reinit is passed as 1
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*/
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if (reinit) {
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int i;
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/* Enable interrupts */
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temp = bdc_readl(bdc->regs, BDC_BDCSC);
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temp |= BDC_GIE;
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bdc_writel(bdc->regs, BDC_BDCSC, temp);
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/* Init scratchpad to 0 */
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memset(bdc->scratchpad.buff, 0, bdc->sp_buff_size);
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/* Initialize SRR to 0 */
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memset(bdc->srr.sr_bds, 0,
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NUM_SR_ENTRIES * sizeof(struct bdc_bd));
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/* clear ep flags to avoid post disconnect stops/deconfigs */
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for (i = 1; i < bdc->num_eps; ++i)
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bdc->bdc_ep_array[i]->flags = 0;
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} else {
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/* One time initiaization only */
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/* Enable status report function pointers */
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bdc->sr_handler[0] = bdc_sr_xsf;
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bdc->sr_handler[1] = bdc_sr_uspc;
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/* EP0 status report function pointers */
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bdc->sr_xsf_ep0[0] = bdc_xsf_ep0_setup_recv;
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bdc->sr_xsf_ep0[1] = bdc_xsf_ep0_data_start;
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bdc->sr_xsf_ep0[2] = bdc_xsf_ep0_status_start;
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}
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}
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/* Free the dynamic memory */
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static void bdc_mem_free(struct bdc *bdc)
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{
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dev_dbg(bdc->dev, "%s\n", __func__);
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/* Free SRR */
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if (bdc->srr.sr_bds)
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dma_free_coherent(bdc->dev,
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NUM_SR_ENTRIES * sizeof(struct bdc_bd),
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bdc->srr.sr_bds, bdc->srr.dma_addr);
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/* Free scratchpad */
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if (bdc->scratchpad.buff)
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dma_free_coherent(bdc->dev, bdc->sp_buff_size,
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bdc->scratchpad.buff, bdc->scratchpad.sp_dma);
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/* Destroy the dma pools */
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dma_pool_destroy(bdc->bd_table_pool);
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/* Free the bdc_ep array */
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kfree(bdc->bdc_ep_array);
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bdc->srr.sr_bds = NULL;
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bdc->scratchpad.buff = NULL;
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bdc->bd_table_pool = NULL;
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bdc->bdc_ep_array = NULL;
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}
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/*
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* bdc reinit gives a controller reset and reinitialize the registers,
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* called from disconnect/bus reset scenario's, to ensure proper HW cleanup
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*/
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int bdc_reinit(struct bdc *bdc)
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{
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int ret;
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dev_dbg(bdc->dev, "%s\n", __func__);
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ret = bdc_stop(bdc);
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if (ret)
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goto out;
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ret = bdc_reset(bdc);
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if (ret)
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goto out;
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/* the reinit flag is 1 */
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bdc_mem_init(bdc, true);
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ret = bdc_run(bdc);
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out:
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bdc->reinit = false;
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return ret;
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}
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/* Allocate all the dyanmic memory */
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static int bdc_mem_alloc(struct bdc *bdc)
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{
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u32 page_size;
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unsigned int num_ieps, num_oeps;
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dev_dbg(bdc->dev,
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"%s() NUM_BDS_PER_TABLE:%d\n", __func__,
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NUM_BDS_PER_TABLE);
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page_size = BDC_PGS(bdc_readl(bdc->regs, BDC_BDCCFG0));
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/* page size is 2^pgs KB */
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page_size = 1 << page_size;
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/* KB */
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page_size <<= 10;
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dev_dbg(bdc->dev, "page_size=%d\n", page_size);
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/* Create a pool of bd tables */
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bdc->bd_table_pool =
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dma_pool_create("BDC BD tables", bdc->dev, NUM_BDS_PER_TABLE * 16,
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16, page_size);
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if (!bdc->bd_table_pool)
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goto fail;
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if (scratchpad_setup(bdc))
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goto fail;
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/* read from regs */
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num_ieps = NUM_NCS(bdc_readl(bdc->regs, BDC_FSCNIC));
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num_oeps = NUM_NCS(bdc_readl(bdc->regs, BDC_FSCNOC));
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/* +2: 1 for ep0 and the other is rsvd i.e. bdc_ep[0] is rsvd */
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bdc->num_eps = num_ieps + num_oeps + 2;
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dev_dbg(bdc->dev,
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"ieps:%d eops:%d num_eps:%d\n",
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num_ieps, num_oeps, bdc->num_eps);
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/* allocate array of ep pointers */
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bdc->bdc_ep_array = kcalloc(bdc->num_eps, sizeof(struct bdc_ep *),
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GFP_KERNEL);
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if (!bdc->bdc_ep_array)
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goto fail;
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dev_dbg(bdc->dev, "Allocating sr report0\n");
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if (setup_srr(bdc, 0))
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goto fail;
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return 0;
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fail:
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dev_warn(bdc->dev, "Couldn't initialize memory\n");
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bdc_mem_free(bdc);
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return -ENOMEM;
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}
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/* opposite to bdc_hw_init */
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static void bdc_hw_exit(struct bdc *bdc)
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{
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dev_dbg(bdc->dev, "%s ()\n", __func__);
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bdc_mem_free(bdc);
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}
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/* Initialize the bdc HW and memory */
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static int bdc_hw_init(struct bdc *bdc)
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{
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int ret;
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dev_dbg(bdc->dev, "%s ()\n", __func__);
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ret = bdc_reset(bdc);
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if (ret) {
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dev_err(bdc->dev, "err resetting bdc abort bdc init%d\n", ret);
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return ret;
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}
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ret = bdc_mem_alloc(bdc);
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if (ret) {
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dev_err(bdc->dev, "Mem alloc failed, aborting\n");
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return -ENOMEM;
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}
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bdc_mem_init(bdc, 0);
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bdc_dbg_regs(bdc);
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dev_dbg(bdc->dev, "HW Init done\n");
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return 0;
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}
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static int bdc_phy_init(struct bdc *bdc)
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{
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int phy_num;
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int ret;
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for (phy_num = 0; phy_num < bdc->num_phys; phy_num++) {
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ret = phy_init(bdc->phys[phy_num]);
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if (ret)
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goto err_exit_phy;
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ret = phy_power_on(bdc->phys[phy_num]);
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if (ret) {
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phy_exit(bdc->phys[phy_num]);
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goto err_exit_phy;
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}
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}
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return 0;
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err_exit_phy:
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while (--phy_num >= 0) {
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phy_power_off(bdc->phys[phy_num]);
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phy_exit(bdc->phys[phy_num]);
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}
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return ret;
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}
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static void bdc_phy_exit(struct bdc *bdc)
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{
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int phy_num;
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for (phy_num = 0; phy_num < bdc->num_phys; phy_num++) {
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phy_power_off(bdc->phys[phy_num]);
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phy_exit(bdc->phys[phy_num]);
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}
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}
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static int bdc_probe(struct platform_device *pdev)
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{
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struct bdc *bdc;
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struct resource *res;
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int ret = -ENOMEM;
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int irq;
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u32 temp;
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struct device *dev = &pdev->dev;
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struct clk *clk;
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int phy_num;
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dev_dbg(dev, "%s()\n", __func__);
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clk = devm_clk_get(dev, "sw_usbd");
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if (IS_ERR(clk)) {
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dev_info(dev, "Clock not found in Device Tree\n");
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clk = NULL;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(dev, "could not enable clock\n");
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return ret;
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}
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bdc = devm_kzalloc(dev, sizeof(*bdc), GFP_KERNEL);
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if (!bdc)
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return -ENOMEM;
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bdc->clk = clk;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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bdc->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(bdc->regs)) {
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dev_err(dev, "ioremap error\n");
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return -ENOMEM;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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spin_lock_init(&bdc->lock);
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platform_set_drvdata(pdev, bdc);
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bdc->irq = irq;
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bdc->dev = dev;
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dev_dbg(dev, "bdc->regs: %p irq=%d\n", bdc->regs, bdc->irq);
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bdc->num_phys = of_count_phandle_with_args(dev->of_node,
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"phys", "#phy-cells");
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if (bdc->num_phys > 0) {
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bdc->phys = devm_kcalloc(dev, bdc->num_phys,
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sizeof(struct phy *), GFP_KERNEL);
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if (!bdc->phys)
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return -ENOMEM;
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} else {
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bdc->num_phys = 0;
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}
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dev_info(dev, "Using %d phy(s)\n", bdc->num_phys);
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for (phy_num = 0; phy_num < bdc->num_phys; phy_num++) {
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bdc->phys[phy_num] = devm_of_phy_get_by_index(
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dev, dev->of_node, phy_num);
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if (IS_ERR(bdc->phys[phy_num])) {
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ret = PTR_ERR(bdc->phys[phy_num]);
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dev_err(bdc->dev,
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"BDC phy specified but not found:%d\n", ret);
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return ret;
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}
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}
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ret = bdc_phy_init(bdc);
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if (ret) {
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dev_err(bdc->dev, "BDC phy init failure:%d\n", ret);
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return ret;
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}
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temp = bdc_readl(bdc->regs, BDC_BDCCAP1);
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if ((temp & BDC_P64) &&
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!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) {
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dev_dbg(dev, "Using 64-bit address\n");
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} else {
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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if (ret) {
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dev_err(dev,
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"No suitable DMA config available, abort\n");
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ret = -ENOTSUPP;
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goto phycleanup;
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|
}
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|
dev_dbg(dev, "Using 32-bit address\n");
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}
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ret = bdc_hw_init(bdc);
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if (ret) {
|
|
dev_err(dev, "BDC init failure:%d\n", ret);
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goto phycleanup;
|
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}
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ret = bdc_udc_init(bdc);
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|
if (ret) {
|
|
dev_err(dev, "BDC Gadget init failure:%d\n", ret);
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|
goto cleanup;
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|
}
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return 0;
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|
|
|
cleanup:
|
|
bdc_hw_exit(bdc);
|
|
phycleanup:
|
|
bdc_phy_exit(bdc);
|
|
return ret;
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|
}
|
|
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static int bdc_remove(struct platform_device *pdev)
|
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{
|
|
struct bdc *bdc;
|
|
|
|
bdc = platform_get_drvdata(pdev);
|
|
dev_dbg(bdc->dev, "%s ()\n", __func__);
|
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bdc_udc_exit(bdc);
|
|
bdc_hw_exit(bdc);
|
|
bdc_phy_exit(bdc);
|
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clk_disable_unprepare(bdc->clk);
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return 0;
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}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
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static int bdc_suspend(struct device *dev)
|
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{
|
|
struct bdc *bdc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
/* Halt the controller */
|
|
ret = bdc_stop(bdc);
|
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if (!ret)
|
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clk_disable_unprepare(bdc->clk);
|
|
|
|
return ret;
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|
}
|
|
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|
static int bdc_resume(struct device *dev)
|
|
{
|
|
struct bdc *bdc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(bdc->clk);
|
|
if (ret) {
|
|
dev_err(bdc->dev, "err enabling the clock\n");
|
|
return ret;
|
|
}
|
|
ret = bdc_reinit(bdc);
|
|
if (ret) {
|
|
dev_err(bdc->dev, "err in bdc reinit\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_PM_SLEEP */
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|
|
|
static SIMPLE_DEV_PM_OPS(bdc_pm_ops, bdc_suspend,
|
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bdc_resume);
|
|
|
|
static const struct of_device_id bdc_of_match[] = {
|
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{ .compatible = "brcm,bdc-v0.16" },
|
|
{ .compatible = "brcm,bdc" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static struct platform_driver bdc_driver = {
|
|
.driver = {
|
|
.name = BRCM_BDC_NAME,
|
|
.pm = &bdc_pm_ops,
|
|
.of_match_table = bdc_of_match,
|
|
},
|
|
.probe = bdc_probe,
|
|
.remove = bdc_remove,
|
|
};
|
|
|
|
module_platform_driver(bdc_driver);
|
|
MODULE_AUTHOR("Ashwini Pahuja <ashwini.linux@gmail.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION(BRCM_BDC_DESC);
|