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2106b21a8a
commit fedb8da963 upstream.
For years I thought all parisc machines executed loads and stores in
order. However, Jeff Law recently indicated on gcc-patches that this is
not correct. There are various degrees of out-of-order execution all the
way back to the PA7xxx processor series (hit-under-miss). The PA8xxx
series has full out-of-order execution for both integer operations, and
loads and stores.
This is described in the following article:
http://web.archive.org/web/20040214092531/http://www.cpus.hp.com/technical_references/advperf.shtml
For this reason, we need to define mb() and to insert a memory barrier
before the store unlocking spinlocks. This ensures that all memory
accesses are complete prior to unlocking. The ldcw instruction performs
the same function on entry.
Signed-off-by: John David Anglin <dave.anglin@bell.net>
Cc: stable@vger.kernel.org # 4.0+
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
33 lines
785 B
C
33 lines
785 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#ifndef __ASSEMBLY__
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/* The synchronize caches instruction executes as a nop on systems in
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which all memory references are performed in order. */
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#define synchronize_caches() __asm__ __volatile__ ("sync" : : : "memory")
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#if defined(CONFIG_SMP)
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#define mb() do { synchronize_caches(); } while (0)
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#define rmb() mb()
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#define wmb() mb()
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#define dma_rmb() mb()
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#define dma_wmb() mb()
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#else
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define dma_rmb() barrier()
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#define dma_wmb() barrier()
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#endif
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#define __smp_mb() mb()
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#define __smp_rmb() mb()
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#define __smp_wmb() mb()
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#include <asm-generic/barrier.h>
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_BARRIER_H */
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