mirror of
https://github.com/brain-hackers/linux-brain.git
synced 2024-06-09 23:36:23 +09:00
bc3d3447b6
Currently if the Foundation model is running ARM Trusted Firmware then the kernel, which is configured to use spin tables, cannot start secondary processors or "power off" the simulation. After adding a couple of labels to the include file and splitting out the spin-table configuration into a header, we add a couple of new headers together with two new DTs (GICv2 + PSCI and GICv3 + PSCI). The new GICv3+PSCI DT has been boot tested, the remaining three (two of which existed prior to this patch) have been "tested" by decompiling the blobs and comparing them against a reference. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
26 lines
403 B
Plaintext
26 lines
403 B
Plaintext
/*
|
|
* ARM Ltd.
|
|
*
|
|
* ARMv8 Foundation model DTS (spin table configuration)
|
|
*/
|
|
|
|
&cpu0 {
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0x8000fff8>;
|
|
};
|
|
|
|
&cpu1 {
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0x8000fff8>;
|
|
};
|
|
|
|
&cpu2 {
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0x8000fff8>;
|
|
};
|
|
|
|
&cpu3 {
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0x8000fff8>;
|
|
};
|