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3d9e764830
This enables DVFS for the Amlogic SM1 based SEI610 board by: - Adding the SM1 SoC OPPs taken from the vendor tree - Selecting the SM1 Clock controller instead of the G12A one - Adding the CPU rail regulator, PWM and OPPs for each CPU nodes. Each power supply can achieve 0.69V to 1.05V using a single PWM output clocked at 666KHz with an inverse duty-cycle. DVFS has been tested by running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of the cpu cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
148 lines
2.5 KiB
Plaintext
148 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include "meson-g12-common.dtsi"
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#include <dt-bindings/power/meson-sm1-power.h>
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/ {
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compatible = "amlogic,sm1";
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <730000>;
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};
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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opp-microvolt = <730000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <730000>;
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};
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opp-667000000 {
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opp-hz = /bits/ 64 <666666666>;
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opp-microvolt = <750000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <770000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <780000>;
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};
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opp-1404000000 {
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opp-hz = /bits/ 64 <1404000000>;
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opp-microvolt = <790000>;
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};
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opp-1512000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <800000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <810000>;
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};
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opp-1704000000 {
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opp-hz = /bits/ 64 <1704000000>;
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opp-microvolt = <850000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <900000>;
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};
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opp-1908000000 {
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opp-hz = /bits/ 64 <1908000000>;
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opp-microvolt = <950000>;
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};
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};
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};
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&cecb_AO {
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compatible = "amlogic,meson-sm1-ao-cec";
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};
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&clk_msr {
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compatible = "amlogic,meson-sm1-clk-measure";
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};
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&clkc {
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compatible = "amlogic,sm1-clkc";
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};
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ðmac {
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power-domains = <&pwrc PWRC_SM1_ETH_ID>;
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};
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&pwrc {
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compatible = "amlogic,meson-sm1-pwrc";
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};
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&vpu {
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power-domains = <&pwrc PWRC_SM1_VPU_ID>;
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};
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&usb {
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power-domains = <&pwrc PWRC_SM1_USB_ID>;
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};
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