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f29cabf240
The snps,reset-gpio bindings are deprecated in favour of the generic "Ethernet PHY reset" bindings. Replace snps,reset-gpio from the ðmac node with reset-gpios in the ethernet-phy node. The old snps,reset-active-low property is now encoded directly as GPIO flag inside the reset-gpios property. snps,reset-delays-us is converted to reset-assert-us and reset-deassert-us. reset-assert-us is the second cell from snps,reset-delays-us while reset-deassert-us was the third cell. Instead of blindly copying the old values (which seems strange since they gave the PHY one second to come out of reset) over this also updates the delays based on the datasheets: - the Realtek RTL8211F PHY needs a 10ms assert delay (the datasheet mentions: "For a complete PHY reset, this pin must be asserted low for at least 10ms") and a 30ms deassert delay (the datasheet mentions: "Wait for a further 30ms (for internal circuits settling time) before accessing the PHY register". This applies to the following boards: GXBB NanoPi K2, GXBB Odroid-C2, GXBB Vega S95 variants, GXBB Wetek variants, GXL P230, GXM Khadas VIM2, GXM Nexbox A1, GXM Q200, GXM RBox Pro boards. - the ICPlus IP101GR PHY needs a 10ms assert delay (the datasheet mentions: "Trst | Reset period | 10ms") and a deassert delay of 10ms as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock output ready after reset released | 10ms"). This applies to the GXBB Nexbox A95X board. - the Micrel KSZ9031 seems to require a 100us delay but use the same (seemingly safe) values from RTL8211F due to lack of a board to verify this. This applies to the GXBB P200 board. The GXBB P201 board is left out from this conversion because it doesn't have a dedicated PHY node (because it's not clear which PHY is used on that board). Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
101 lines
2.0 KiB
Plaintext
101 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2016 Andreas Färber
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* Copyright (c) 2016 BayLibre, Inc.
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* Author: Kevin Hilman <khilman@kernel.org>
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*/
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/dts-v1/;
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#include "meson-gxbb-p20x.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "amlogic,p200", "amlogic,meson-gxbb";
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model = "Amlogic Meson GXBB P200 Development Board";
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avdd18_usb_adc: regulator-avdd18_usb_adc {
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compatible = "regulator-fixed";
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regulator-name = "AVDD18_USB_ADC";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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adc_keys {
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compatible = "adc-keys";
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io-channels = <&saradc 0>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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button-home {
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label = "Home";
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linux,code = <KEY_HOME>;
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press-threshold-microvolt = <900000>; /* 50% */
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};
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button-esc {
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label = "Esc";
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linux,code = <KEY_ESC>;
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press-threshold-microvolt = <684000>; /* 38% */
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};
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button-up {
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label = "Volume Up";
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linux,code = <KEY_VOLUMEUP>;
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press-threshold-microvolt = <468000>; /* 26% */
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};
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button-down {
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label = "Volume Down";
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linux,code = <KEY_VOLUMEDOWN>;
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press-threshold-microvolt = <252000>; /* 14% */
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};
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button-menu {
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label = "Menu";
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linux,code = <KEY_MENU>;
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press-threshold-microvolt = <0>; /* 0% */
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};
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};
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};
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ðmac {
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status = "okay";
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pinctrl-0 = <ð_rgmii_pins>;
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pinctrl-names = "default";
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phy-handle = <ð_phy0>;
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phy-mode = "rgmii";
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amlogic,tx-delay-ns = <2>;
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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eth_phy0: ethernet-phy@3 {
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/* Micrel KSZ9031 (0x00221620) */
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reg = <3>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio_intc>;
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/* MAC_INTR on GPIOZ_15 */
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interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&i2c_B {
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status = "okay";
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pinctrl-0 = <&i2c_b_pins>;
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pinctrl-names = "default";
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};
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&saradc {
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status = "okay";
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vref-supply = <&avdd18_usb_adc>;
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};
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